IS27LV256
IS27LV256
32,768 x 8 LOW VOLTAGE CMOS EPROM
ISSI
ISSI
®
®
ADVANCE INFORMATION
APRIL 1998
FEATURES
•
•
•
•
Single 2.7V to 3.6V power supply
Fast access time: 70 ns
JEDEC-approved pinout
Low power consumption (2.7 to 3.6 Vcc)
— 20
µA
(max) standby current
— 8 mA (max) active current at 5 MHz
• High-speed write programming
— Typically less than eight seconds
• Industrial and commercial temperature ranges
available
• Standard 28-pin DIP and TSOP, and 32-pin
PLCC packages
DESCRIPTION
The
ISSI
IS27LV256 is a low power, high-speed 256K-bit
CMOS (32K-word by 8-bit) CMOS Programmable Read-Only
Memory. It utilizes the standard JEDEC pinout making it
functionally compatible with the IS27C256 EPROM.
The superior access time combined with low power consump-
tion is the result of innovative design and process technology.
If the device is constantly accessed at 5 MHz, then the
maximum power consumption is 36 mW for a 2.7V supply.
These power ratings are significantly lower than the standard
IS27C256 EPROM.
The IS27LV256 uses
ISSI
'
s write programming algorithm
which allows the entire chip to be programmed in typically less
than thirty seconds.
This product is available in a One-Time Programmable (OTP)
PDIP, PLCC, and TSOP packages over commercial and
industrial temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
V
PP
DQ0-DQ7
8
OE
CE
OUTPUT ENABLE
CHIP ENABLE
AND
PROG LOGIC
OUTPUT
BUFFERS
Y
DECODER
A0-A14
Y
GATING
15
X
DECODER
262,144-BIT
CELL MATRIX
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EP006-0B
04/15/98
1
IS27LV256
PIN CONFIGURATIONS
28-Pin DIP
V
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
ISSI
PIN DESCRIPTIONS
A0-A14
Address Inputs
Chip Enable Input
Data Inputs/Outputs
Output Enable Input/
Program Voltage Input
Power Supply Voltage
Program Supply Voltage
Ground
No Internal Connection
®
CE
DQ0-DQ7
OE
Vcc
V
PP
GND
NC
32-Pin PLCC
VCC
A12
A14
A13
V
PP
NC
A7
28-Pin TSOP
INDEX
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE
A10
CE
DQ7
DQ6
OE
A11
A9
A8
A13
A14
V
CC
V
PP
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
14
DQ1
15
DQ2
16
GND
17
NC
18
DQ3
19
DQ4
20
DQ5
2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EP006-0B
04/15/98
IS27LV256
FUNCTIONAL DESCRIPTION
Programming the IS27LV256
Upon delivery, the IS27LV256 has 262,144 bits in the
"ONE", or HIGH state. "ZEROs" are loaded into the
IS27LV256 through the procedure of programming.
The programming mode is entered when 12.5
±
0.25V is
applied to the V
PP
pin, V
CC
= 6V,
CE
is at V
IL
and
OE
is at
V
IH
. For programming, the data to be programmed is
applied eight bits in parallel to the data output pins.
The write programming algorithm reduces programming
time by using 100
µs
programming pulses followed by a
byte verification to determine whether the byte has been
successfully programmed. If the data does not verify, an
additional pulse is applied for a maximum of 25 pulses.
This process is repeated while sequencing through each
address of the EPROM.
The write programming algorithm programs and verifies at
V
CC
= 6V and V
PP
= 12.5V. After the final address is
completed, all byte are compared to the original data with
V
CC
= 5.25V.
Program Inhibit
Programming of multiple IS27LV256s in parallel with dif-
ferent data is also easily accomplished. Except for
CE
, all
like inputs of the parallel IS27LV256 may be common. A
TTL low-level program pulse applied to an IS27LV256
CE
input with V
PP
= 12.5
±
0.25V will program that IS27LV256.
A high-level
CE
input inhibits the other IS27LV256 from
being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with
CE
at V
IH
and
OE
at V
IL
with V
PP
= 12.5V
±
0.25V.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and type. This mode is intended for use by programming
equipment for the purpose of automatically matching the
device to be programmed with its corresponding program-
ming algorithm. This mode is functional in the 25°C
±
5°C
ambient temperature range that is required when pro-
gramming the IS27LV256.
To activate this mode, the programming equipment must
force 12.0
±
0.5V on address line A9 of the IS27LV256.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from V
IL
to V
IH
.
All other address lines must be held at V
IL
during auto
select mode.
ISSI
®
Byte 0 (A0 = V
IL
) represents the manufacturer code, and
byte 1 (A0 = V
IH
), the device identifier code. For the
IS27LV256, these two identifier bytes are given in the
Mode Select table. All identifiers manufacturer and device
codes will possess odd parity, with the MSB (DQ7) defined
as the parity bit.
Read Mode
The IS27LV256 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (
CE
) is the power control and should
be used for device selection. Assuming that addresses are
stable, address access time (t
ACC
) is equal to the delay
from
CE
to output (t
CE
). Output Enable (
OE
) is the output
control and should be used to get data to the output pins,
independent of device selection. Data is available at the
outputs t
OE
after the falling edge of
OE
assuming that
CE
has been LOW and addresses have been stable for at
least t
ACC
– t
OE
.
Standby Mode
The IS27LV256 has a standby mode which reduces the
maximum V
CC
active current. It is placed in standby mode
when
CE
is at V
IH
. The amount of current drawn in standby
mode depends on the frequency and the number of
address pins switching. The IS27LV256 is specified with
50% of the address lines toggling at 5 MHz. A reduction of
the frequency or quantity of address lines toggling will
significantly reduce the actual standby current.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EP006-0B
04/15/98
3
IS27LV256
Output OR-Tieing
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation, and
2. Assurance that output bus contention will not
occur.
It is recommended that
CE
be decoded and used as the
primary device-selecting function, while
OE
be made a
common connection to all devices in the array and con-
nected to the READ line from the system control bus. This
assures that all deselected memory devices are in their
low-power standby mode and that the output pins are only
active when data is desired from a particular memory
device.
ISSI
®
System Applications
During the switch between active and standby conditions,
transient current peaks are produced on the rising and
falling edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output capaci-
tance loading of the device at a minimum, a 0.1
µF
ceramic
capacitor (high-frequency, low inherent inductance) should
be used on each device between V
CC
and GND to mini-
mize transient effects. In addition, to overcome the voltage
drop caused by the inductive effects of the printed circuit
board traces on EPROM arrays, a 4.7
µF
bulk electrolytic
capacitor should be used between V
CC
and GND for each
eight devices. The location of the capacitor should be
close to where the power supply is connected to the array.
TRUTH TABLE
(1,2,4)
Mode
Read
Output Disable
(6)
Standby
Program
Program Verify
Program Inhibit
Auto Select
(3,5)
Manufacturer Code
Device Code
CE
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
V
IL
V
IL
OE
V
IL
V
IH
X
V
IH
V
IL
V
IH
V
IL
V
IL
V
PP
V
CC
V
CC
V
CC
V
PP
V
PP
V
PP
V
CC
V
CC
A0
X
X
X
X
X
X
V
IL
V
IH
A9
X
X
X
X
X
X
V
H
V
H
Outputs
D
OUT
Hi-Z
Hi-Z
D
IN
D
OUT
Hi-Z
D5H
10H
Notes:
1. V
H
= 12.0V
±
0.5V.
2. X = Either V
IH
or V
IL
.
3. A1-A8 = A10-A14 = V
IL
.
4. See DC Programming Characteristics for V
PP
voltage during programming.
5. The IS27LV256 can use the same write algorithm during program as other IS27LV256 devices.
6. Read, output disable, and standby modes require 2.7V
≤
Vcc
≤
3.6V, 4.5V
≤
Vcc
≤
5.5V.
LOGIC SYMBOL
15
A0-A14
8
DQ0-DQ7
CE
OE
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EP006-0B
04/15/98
IS27LV256
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Parameter
Terminal Voltage with Respect to GND
All pins except A9 and V
PP
V
PP
A9
V
CC
Ambient Temperature with Power Applied
Storage Temperature (OTP)
Storage Temperature (All others)
Value
–0.6 to V
CC
+ 0.5
(2)
V
CC
– 0.3 to 13.5
(2,3)
–0.6 to 13.5
(2,3)
–0.6 to 7.0
(2)
–65 to +125
–65 to +125
–65 to +150
Unit
V
V
V
V
°C
°C
°C
ISSI
®
T
A
T
STG
T
STG
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods less than 10
ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than
10 ns.
3. Maximum DC voltage on A9 or V
PP
may overshoot to +13.5V for periods less than 10 ns.
OPERATING RANGE
Range
Commercial
Industrial
(1)
Ambient Temperature
0°C to +70°C
–40°C to +85°C
Vcc
2.7V to 3.6V
2.7V to 3.6V
Note:
1. Operating ranges define those limits between which the
functionally of the device is guaranteed.
DC ELECTRICAL CHARACTERISTICS
(1,2,3)
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(4)
Input LOW Voltage
(4)
Input Load Current
Output Leakage Current
V
IN
= 0V to +V
CC
V
OUT
= 0V to +V
CC
Test Conditions
V
CC
= Min., I
OH
= –400
µA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.4
—
2.0
–0.3
—
—
Max.
—
0.4
V
CC
+ 0.5
0.8
1
5
Unit
V
V
V
V
µA
µA
Notes:
1. V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. Never try to force V
PP
LOW to 1V
below V
CC
. Manufacturer suggests to tie V
PP
and V
CC
together during the READ operation.
2.
Caution:
the IS27LV256 must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied.
3. Minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V for periods less than 10 ns.
Maximum DC voltage on output pins is V
CC
+ 0.5V which may overshoot to V
CC
+ 2.0V for periods less than 10 ns.
4. Tested under static DC conditions.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EP006-0B
04/15/98
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
