HY27UF084G2M Series
4Gbit (512Mx8bit) NAND Flash
4Gb NAND FLASH
HY27UF084G2M
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.7 / Dec. 2006
1
HY27UF084G2M Series
4Gbit (512Mx8bit) NAND Flash
Document Title
4Gbit (512Mx8bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Add ULGA Package.
- Figures & texts are added.
2) Add Read ID Table
3) Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
LI,
I
LO
)
Before
VIN=VOUT=0 to 3.6V
History
Draft Date
Dec. 2004
Remark
Initial
After VIN=VOUT=0 to Vcc (max)
0.1
3) Change AC Conditions table
4) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
4) Edit System Interface Using CE don’t care.
5) Add Marking Information.
6) Correct Address Cycle Map.
7) Correct PKG dimension (TSOP PKG)
CP
Before
After
0.050
0.100
Aug. 08. 2005
Preliminary
8) Delete the 1.8V device’s features.
Rev. 0.7 / Dec. 2006
2
HY27UF084G2M Series
4Gbit (512Mx8bit) NAND Flash
Revision History
Revision
No.
1) Change AC Characteristics
tR
Before
After
20
25
tCLS
0.2
Before
After
12
15
tAR
10
15
tWP
12
15
tDS
12
15
tREA
18
20
tWC
25
30
tRHZ
30
50
tADL
70
100
tCHZ
30
50
tRP
12
15
tCEA
25
35
tRC
25
30
Oct. 08. 2005
Preliminary
-Continued-
History
Draft Date
Remark
2) Add tCRRH (100ns, Min)
- tCRRH : Cache Read RE High
3) Change 3rd Read ID
- 3rd Read ID is changed to 80h
- 3rd Byte of Device Identifier Table is added.
4) Change NOP
- Number of partial Program Cycle in the same page is changed to 4.
1) Change AC Characteristics
tREA
0.3
Before
After
20
25
tCEA
35
30
tCS
20
25
Nov. 16. 2005
Preliminary
0.4
0.5
0.6
0.7
1) Add ECC algorithm. (1bit/512bytes)
2) Change NOP
3) Correct Read ID naming
1) Delet Preliminary.
1) Correct copy back function.
1) Delete PRE function.
2) Delete Lock & Unlock function.
3) Delete Auto Read function.
Jun. 20. 2006
Jul. 10. 2006
Oct. 02. 2006
Dec. 26. 2006
Preliminary
Rev. 0.7 / Dec. 2006
3
HY27UF084G2M Series
4Gbit (512Mx8bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle : Manufacturer Code
- 2nd cycle: Device Code
CHIP ENABLE DON'T CARE
- Simple interface with microcontroller
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 4,096 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27UF084G2M
DATA INTEGRITY
- 100,000 Program/Erase cycles (with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27UF084G2M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UF084G2M-T (Lead)
- HY27UF084G2M-TP (Lead Free)
- HY27UF084G2M-UP
: 52-ULGA (12 x 17 x 0.65 mm)
- HY27UF084G2M-UP (Lead Free)
- Program/Erase locked during Power transitions
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V : HY27UF084G2M
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
PAGE READ / PROGRAM
- Random access: 25us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
Rev. 0.7 / Dec. 2006
4
HY27UF084G2M Series
4Gbit (512Mx8bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27UF084G2M series is a 512Mx8bit with spare 16Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 4096 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UF084G2M extended reliability of 100K program/
erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HYNIX HY27UF084G2M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27UF084G2M
ORIZATION
x8
VCC RANGE
2.7V - 3.6 Volt
PACKAGE
48TSOP1 / 52-ULGA
Rev. 0.7 / Dec. 2006
5
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