NCD57001
Isolated High Current IGBT
Gate Driver
NCD57001 is a high−current single channel IGBT driver with
internal galvanic isolation, designed for high system efficiency and
reliability in high power applications. Its features include
complementary inputs, open drain FAULT and Ready outputs, active
Miller clamp, accurate UVLOs, DESAT protection, and soft turn−off
at DESAT. NCD57001 accommodates both 5 V and 3.3 V signals on
the input side and wide bias voltage range on the driver side including
negative voltage capability. NCD57001 provides > 5 kVrms
(UL1577 rating) galvanic isolation and > 1200 V
iorm
(working
voltage) capabilities. NCD57001 is available in the wide−body
SOIC−16 package with guaranteed 8 mm creepage distance between
input and output to fulfill reinforced safety insulation requirements.
Features
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1
SOIC−16 WB
CASE 751G−03
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MARKING DIAGRAM
16
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages
Low Output Impedance for Enhanced IGBT Driving
Short Propagation Delays with Accurate Matching
Active Miller Clamp to Prevent Spurious Gate Turn−on
DESAT Protection with Programmable Delay
Negative Voltage (Down to
−9
V) Capability for DESAT
Soft Turn Off During IGBT Short Circuit
IGBT Gate Clamping During Short Circuit
IGBT Gate Active Pull Down
Tight UVLO Thresholds for Bias Flexibility
Wide Bias Voltage Range including Negative VEE2
3.3 V to 5 V Input Supply Voltage
Designed for AEC−Q100 Certification
5000 V Galvanic Isolation (to meet UL1577 Requirements)
1200 V Working Voltage (per VDE0884−10 Requirements)
High Transient Immunity
High Electromagnetic Immunity
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “
G”,
may or may not be present.
PIN ASSIGNMENT
VEE2A
DESAT
GND2
N/C
VDD2
OUT
CLAMP
VEE2
GND1
VDD1
RST
FLT
RDY
IN−
Typical Applications
Solar Inverters
Motor Control
Uninterruptible Power Supplies (UPS)
Industrial Power Supplies
Welding
IN+
GND1A
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2018
February, 2019
−
Rev. 2
1
Publication Order Number:
NCD57001/D
NCD57001
VDD1
VDD1
UVLO1
VDD2
UVLO2
+
IN−
IN+
VEE2
STO
−
V
CLAMP−THR
CLAMP
VDD1
OUT
RDY
Logic
Logic
1
VDD2
I
DESAT−CHG
+
RST
VDD1
−
V
DESAT−THR
DESAT
VDD1
FLT
GND1
1
2
GND2
GND1A
VEE2
VEE2A
Figure 1. Simplified Block Diagram
V1
+V2
VDD1
IN+
IN−
VDD2
DESAT
OUT
RDY
FLT
RST
GND1
CLAMP
VEE2
GND2
−V3
GND1
GND2
Figure 2. Simplified Application Schematics
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2
NCD57001
PIN DESCRIPTION
Pin Name
V
EE2A
V
EE2
No.
1
8
2
I/O
Power
Description
Output side negative power supply. A good quality bypassing capacitor is required from these pins
to GND2 and should be placed close to the pins for best results. Connect it to GND2 for unipolar
supply application.
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DESAT
I/O
Input for detecting the desaturation of IGBT due to a short circuit condition. An internal constant
current source I
DESAT−CHG
charging an external capacitor connected to this pin allows a
programmable blanking delay every ON cycle before DESAT fault is processed, thus preventing
false triggering. When the DESAT voltage goes up and reaches V
DESAT−THR
, the output is driven
low. Further, the /FLT output is activated, please refer to Figure 5 on page 9.
A 5
ms
mute time apply to IN+ and IN− once DESAT occurs.
GND2
N/C
3
4
5
Power
−
Output side gate drive reference connecting to IGBT emitter or FET source.
Not connected.
V
DD2
Power
Output side positive power supply. The operating range for this pin is from UVLO2 to its maximum
allowed value. A good quality bypassing capacitor is required from this pin to GND2 and should be
placed close to the pins for best results.
Driver output that provides the appropriate drive voltage and source/sink current to the IGBT/FET
gate. OUT is actively pulled low during start−up and under Fault conditions.
OUT
6
7
O
CLAMP
I/O
Provides clamping for the IGBT/FET gate during the off period to protect it from parasitic turn−on.
Its internal N FET is turned on when the voltage of this pin falls below V
EE2
+ V
CLAMP−THR
. It is to
be tied directly to IGBT/FET gate with minimum trace length for best results.
Input side ground reference.
GND1
9
Power
16
10
IN+
I
Non inverted gate driver input. It is internally clamped to V
DD1
and has a pull−down resistor of
50 kW to ensure that output is low in the absence of an input signal. A minimum positive going
pulse−width is required at IN+ before OUT responds.
IN−
11
I
Inverted gate driver input. It is internally clamped to V
DD1
and has a pull−up resistor of 50 kW to
ensure that output is low in the absence of an input signal. A minimum negative going pulse−width
is required at IN− before OUT responds.
Power good indication output, active high when V
DD2
is good. There is an internal 50 kW pull−up
resistor connected to this pin. Multiple of them from different drivers can be ”OR”ed together.
If a low RDY event is triggered by UVLO2, the maximum low duration for RDY is 200 ns.
OUT remains low when RDY is low. Short time delay may apply. See Figure 4 on page 8 for
details.
Fault output (active low) that allows communication to the main controller that the driver has
encountered a desaturation condition and has deactivated the output.
Reset input with an internal 50 kW pull−up resistor, active low to reset fault latch.
Input side power supply (3.3 V to 5 V).
RDY
12
O
/FLT
13
14
15
O
I
/RST
V
DD1
Power
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3
NCD57001
ABSOLUTE MAXIMUM RATINGS
(Over operating free−air temperature range unless otherwise noted) (Note 1)
Symbol
V
DD1
−GND1
V
DD2
−GND2
V
EE2
−GND2
V
DD2
−V
EE2
(V
MAX2
)
V
OUT
I
PK−SRC
I
PK−SNK
I
PK−CLAMP
t
CLP
V
LIM
−GND1
I
LIM
−GND1
V
DESAT
−GND2
V
CLAMP
−GND2
P
D
V
ISO
T
J(max)
T
STG
ESD
HBM
ESD
CDM
MSL
T
SLD
Supply voltage, input side
Positive Power Supply, output side
Negative Power Supply, output side
Differential Power Supply, output side
Gate−driver output voltage
Gate−driver output sourcing current
(maximum pulse width = 10
ms,
maximum duty cycle = 0.2%, V
MAX2
= 20 V)
Gate−driver output sinking current
(maximum pulse width = 10
ms,
maximum duty cycle = 0.2%, V
MAX2
= 20 V)
Clamp sinking current
(maximum pulse width = 10
ms,
maximum duty cycle = 0.2%, V
CLAMP
= 3 V)
Maximum Short Circuit Clamping Time (I
OUT_CLAMP
= 500 mA)
Voltage at IN+, IN−, /RST, /FLT, RDY
Output current of /FLT, RDY
Desat Voltage (Note 2)
Clamp Voltage
Power Dissipation (Note 3)
Input to Output Isolation Voltage
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model (Note 4)
ESD Capability, Charged Device Model (Note 4)
Moisture Sensitivity Level
Lead Temperature Soldering Reflow, Pb−Free Versions (Note 5)
Parameter
Minimum
−0.3
−0.3
−10
0
V
EE2
−
0.3
−
−
−
−
−0.3
−
−9
V
EE2
−
0.3
−
−1200
−40
−65
−
−
−
−
Maximum
6
25
0.3
25
V
DD2
+ 0.3
7.8
7.1
2.5
10
V
DD1
+ 0.3
10
V
DD2
+ 0.3
V
DD2
+ 0.3
1400
1200
150
150
±2
±2
2
260
Unit
V
V
V
V
V
A
A
A
ms
V
mA
V
V
mW
V
°C
°C
kV
kV
−
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. The minimum value is verified by characterization with a single pulse of 100 mA for 100
ms.
3. The value is estimated for ambient temperature 25°C and junction temperature 150°C, 650 mm
2
, 1 oz copper, 2 surface layers and 2 internal
power plane layers. Power dissipation is affected by the PCB design and ambient temperature.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
Latchup Current Maximum Rating:
≤100
mA per JEDEC standard: JESD78, 25°C
5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Symbol
R
qJA
Parameter
Thermal Resistance, Junction−to−Air
Conditions
100 mm
2
, 1 oz Copper, 1 Surface Layer
650 mm
2
, 1 oz Copper, 2 Surface Layers and
2 Internal Power Plane Layers
Value
150
84
Unit
°C/W
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4
NCD57001
OPERATING RANGES
(Note 6)
Symbol
V
DD1
−GND1
V
DD2
−GND2
V
EE2
−GND2
V
DD2
−V
EE2
(V
MAX2
)
V
IL
V
IH
|dV
ISO
/dt|
T
A
Parameter
Supply voltage, input side
Positive Power Supply, output side
Negative Power Supply, output side
Differential Power Supply, output side
Low level input voltage at IN+, IN−, /RST
High level input voltage at IN+, IN−, /RST
Common Mode Transient Immunity (1500 V)
Ambient Temperature
Min
UVLO1
UVLO2
−10
0
0
0.7 X V
DD1
100
−40
Max
5.5
24
0
24
0.3 X V
DD1
V
DD1
−
125
Unit
V
V
V
V
V
V
kV/ms
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
ELECTRICAL CHARACTERISTICS
(V
DD1
= 5 V, V
DD2
= 15 V, V
EE2
=
−8
V. For typical values T
A
= 25°C, for min/max values,
T
A
is the operating ambient temperature range that applies, unless otherwise noted)
Symbol
VOLTAGE SUPPLY
V
UVLO1−OUT−ON
V
UVLO1−OUT−OFF
V
UVLO1−HYST
V
UVLO2−OUT−ON
V
UVLO2−OUT−OFF
V
UVLO2−HYST
I
DD1−0
I
DD1−100
I
DD2−0
I
DD2−100
I
EE2−0
I
EE2−100
UVLO1 Output Enabled
UVLO1 Output Disabled
UVLO1 Hysteresis
UVLO2 Output Enabled
UVLO2 Output Disabled
UVLO2 Hysteresis
Input Supply Quiescent Current
Output Low
Input Supply Quiescent Current
Output High
Output Positive Supply Quiescent
Current, Output Low
Output Positive Supply Quiescent
Current, Output High
Output Negative Supply
Quiescent Current, Output Low
Output Negative Supply
Quiescent Current, Output High
IN+ = Low, IN− = Low
RDY = High, /FLT = High
IN+ = High, IN− = Low
RDY = High, /FLT = High
IN+ = Low, IN− = Low
RDY = High, /FLT = High, no load
IN+ = High, IN− = Low
RDY = High, /FLT = High, no load
IN+ = High, IN− = Low, no load
IN+ = High, IN− = Low, no load
−
−
0.4
0.2
2
2
mA
mA
−
3.6
6
mA
−
3.3
4
mA
−
4.8
6
mA
−
2.4
0.125
13.2
12.2
−
−
−
−
−
13.5
12.5
1
1
2
3
−
−
13.8
12.8
V
V
V
V
V
V
mA
Parameter
Test Condition
Min
Typ
Max
Unit
LOGIC INPUT AND OUTPUT
V
IL
V
IH
V
IN−HYST
I
IN−L
, I
RST−L
I
IN+H
IN+, IN−, /RST Low Input Voltage
IN+, IN−, /RST High Input Voltage
Input Hysteresis Voltage
IN−, /RST Input Current
(50 kW pull−up resistor)
IN+ Input Current
(50 kW pull−down resistor)
V
IN−
/V
RST
= 0 V
V
IN+
= 5 V
−
0.7 x
V
DD1
−
−
−
−
−
0.15 x
V
DD1
−100
100
0.3 x
V
DD1
−
−
−
−
V
V
V
mA
mA
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