CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
4. Limits should be considered typical and are not production tested.
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
VCC SUPPLY CURRENT (Note 4)
No Load Switching Supply Current
I
VCC
I
VCC
I
UVCC
ISL6622CBZ and ISL6622IBZ,
f
PWM
= 300kHz, V
VCC
= 12V
ISL6622CRZ and ISL6622IRZ,
f
PWM
= 300kHz, V
VCC
= 12V
ISL6622CBZ and ISL6622IBZ, PWM
Transition from 0V to 2.5V
ISL6622CRZ and ISL6622IRZ, PWM
Transition from 0V to 2.5V
-
-
-
-
-
-
8.2
6.2
2.0
5.7
5
0.7
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Standby Supply Current
I
VCC
I
VCC
I
UVCC
POWER-ON RESET
VCC Rising Threshold
VCC Falling Threshold
LVCC Rising Threshold (Note 4)
LVCC Falling Threshold (Note 4)
PWM INPUT (See “TIMING DIAGRAM” on page 6)
Input Current (Note 4)
I
PWM
V
PWM
= 5V
V
PWM
= 0V
PWM Rising Threshold (Note 4)
PWM Falling Threshold (Note 4)
Three-State Lower Gate Falling Threshold (Note 4)
Three-State Lower Gate Rising Threshold (Note 4)
Three-State Upper Gate Rising Threshold (Note 4)
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
-
-
-
-
-
-
-
500
-430
3.4
1.6
1.6
1.1
3.2
-
-
-
-
-
-
-
µA
µA
V
V
V
V
V
6.25
4.8
-
-
6.45
5.0
4.4
3.4
6.70
5.25
-
-
V
V
V
V
FN6470 Rev 2.00
October 30, 2008
Page 4 of 12
ISL6622
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested
(Continued)
SYMBOL
TEST CONDITIONS
VCC = 12V
t
RU
t
RL
t
FU
t
FL
t
PDHU
t
PDHL
t
PDLU
t
PDLL
t
LG_ON_DM
I
U_SOURCE
I
U_SINK
R
U_SINK
I
L_SOURCE
I
L_SINK
R
L_SINK
V
VCC
= 12V, 3nF Load, 10% to 90%
V
VCC
= 12V, 3nF Load, 10% to 90%
V
VCC
= 12V, 3nF Load, 90% to 10%
V
VCC
= 12V, 3nF Load, 90% to 10%
V
VCC
= 12V, 3nF Load, Adaptive
V
VCC
= 12V, 3nF Load, Adaptive
V
VCC
= 12V, 3nF Load
V
VCC
= 12V, 3nF Load
V
VCC
= 12V
V
VCC
= 12V, 3nF Load
V
VCC
= 12V, 3nF Load
20mA Sink Current
V
VCC
= 12V, 3nF Load
V
VCC
= 12V, 3nF Load
20mA Sink Current
MIN
-
-
-
-
-
-
-
-
-
-
230
TYP
2.8
26
18
18
12
20
10
10
10
60
330
MAX
-
-
-
-
-
-
-
-
-
-
450
UNITS
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
Three-State Upper Gate Falling Threshold (Note 4)
UGATE Rise Time (Note 4)
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
Diode Braking Holdoff Time (Note 4)
Minimum LGATE ON-Time At Diode Emulation
OUTPUT (Note 4)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
t
UG_OFF_DB
V
VCC
= 12V
-
-
-
-
-
-
-
-
1.25
2.0
2
1.35
2
1.35
3
0.90
-
-
-
-
-
-
-
-
A
A
A
A
R
U_SOURCE
20mA Source Current
R
L_SOURCE
20mA Source Current
Functional Pin Description
PACKAGE PIN #
SOIC
1
2
DFN
1
2
PIN
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
This pin sets the LG drive voltage in PSI mode.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see the three-state PWM Input section on page 6 for further details. Connect this pin to the PWM output of the
controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
This pin provides power for the LGATE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin provides power to the upper gate drive. Its operating range is +5V to 12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC and to the LDO for the
lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
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