Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> ISPGAL22V10AC-5LNN

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ISPGAL22V10AC-5LNN: 产品描述EE PLD, 5ns, CMOS, QFN-32; 产品类别可编程逻辑器件可编程逻辑; 文件大小261KB，共17页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com

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ISPGAL22V10AC-5LNN概述

EE PLD, 5ns, CMOS, QFN-32

ISPGAL22V10AC-5LNN规格参数

参数名称	属性值
厂商名称	Lattice(莱迪斯)
零件包装代码	QFN
包装说明	HVQCCN,
针数	32
Reach Compliance Code	unknown
ECCN代码	EAR99
最大时钟频率	143 MHz
JESD-30 代码	S-XQCC-N32
长度	5 mm
湿度敏感等级	3
专用输入次数	11
I/O 线路数量	10
端子数量	32
组织	11 DEDICATED INPUTS, 10 I/O
输出函数	MACROCELL
封装主体材料	UNSPECIFIED
封装代码	HVQCCN
封装形状	SQUARE
封装形式	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）	260
可编程逻辑类型	EE PLD
传播延迟	5 ns
认证状态	Not Qualified
座面最大高度	1 mm
最大供电电压	1.95 V
最小供电电压	1.65 V
标称供电电压	1.8 V
表面贴装	YES
技术	CMOS
端子形式	NO LEAD
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	5 mm
Base Number Matches	1

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Wor

ld's

Fast

Sma t &

lles

SPLD t

December 2008

ispGAL22V10AV/B/C

In-System Programmable Low Voltage

´®

CMOS PLD Generic Array Logic

Data Sheet

Features

■

High Performance

• t

= 2.3ns propagation delay

• f

MAX

= 455 MHz maximum operating frequency

• t

= 2ns maximum from clock input to data

output

• t

= 1.3 ns clock set-up time

Introduction

The ispGAL22V10A is manufactured using Lattice

Semiconductor’s advanced E

CMOS process, which

combines CMOS with Electrically Erasable (E

) ﬂoating

gate technology. With an advanced E

low-power cell

and full CMOS logic approach, the ispGAL22V10A fam-

ily offers fast pin-to-pin speeds, while simultaneously

delivering low standby power without requiring any

“turbo bits” or other traditional power management

schemes. The ispGAL22V10A can interface with both

3.3V, 2.5V and 1.8V signal levels.

The ispGAL22V10A is functionally compatible with the

ispGAL22LV10, GAL22LV10 and GAL22V10.

■

Low Power

• 1.8V core E

CMOS

technology

• Typical standby power <300µW

(ispGAL22V10AC)

• CMOS design techniques provide low static and

dynamic power

■

Space-Saving Packaging

• Available in 32-pin QFNS (Quad Flat-pack,

No lead, Saw-singulated) package 5mm x 5mm

body size

Figure 1. Functional Block Diagram

I/CLK

RESET

■

Easy System Integration

• Operation with 3.3V (ispGAL22V10AV), 2.5V

(ispGAL22V10AB) or 1.8V (ispGAL22V10AC)

supplies

• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

• 5V tolerant I/O for LVCMOS 3.3 interface

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Lead-free package option

• Programmable output slew rate

• 3.3V PCI compatible

OLMC

I/O

OLMC

I/O

OLMC

I/O

PROGRAMMABLE

AND-ARRAY

(132X44)

OLMC

I/O

OLMC

I/O

■

In-System Programmable

• IEEE 1149.1 boundary scan testable

• 3.3V/2.5V/1.8V in-system programmable

(ISP™) using IEEE 1532 compliant interface

OLMC

I/O

OLMC

I/O

■

CELL TECHNOLOGY

• In-system programmable logic

• 100% tested/100% yields

• High speed electrical erasure (<50ms)

OLMC

I/O

OLMC

I/O

■

Applications Include

•

DMA control

State machine control

High speed graphics processing

Software-driven hardware conﬁguration

TDO

TDI

TMS

TCK

PROGRAMMING

LOGIC

OLMC

I/O

PRESET

■

Boundary Scan USERCODE Register

• Supports electronic signature

1. Use 32-pin QFNS package for all new designs. Refer to PCN

#13A-08 for 32-pin QFN package discontinuance.

brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without

notice.

www.latticesemi.com

isp22v10a_03.0

Lattice Semiconductor

ispGAL22V10AV/B/C Data Sheet

ispGAL Architecture

Output Logic Macrocell (OLMC)

The ispGAL22V10A has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs

have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve

product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen

product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional

product-term dedicated to output enable control.

The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or

registered mode. This allows each output to be individually conﬁgured as either active high or active low.

The ispGAL22V10A has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset

(SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to

zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on

the rising edge of the next clock pulse after this product term is asserted.

NOTE: The AR and SP product terms will force the Q output of the ﬂip-ﬂop into the same state regardless of the

polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a

high or low at the output pin, depending on the pin polarity chosen.

Figure 2. Output Logic Macrocell

CLK

4 TO 1

MUX

2 TO 1

MUX

Output Logic Macrocell Conﬁgurations

Each of the Macrocells of the ispGAL22V10A has two primary functional modes: registered, and combinatorial I/O.

The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic com-

piler. Each of these two primary modes, and the bit settings required to enable them, are described below and on

the following page.

Registered

In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-

type ﬂip-ﬂop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive

either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for

each OLMC, and can therefore be deﬁned by a logic equation. The D ﬂip-ﬂop’s /Q output is fed back into the AND

array, with both the true and complement of the feedback available as inputs to the AND array.

Lattice Semiconductor

ispGAL22V10AV/B/C Data Sheet

Electronic Signature

An electronic signature (ES) is provided in every ispGAL22V10A device. It contains 32 bits of reprogrammable

memory that can contain user-deﬁned data. Some uses include user ID codes, revision numbers, or inventory con-

trol. The signature data is always available to the user independent of the state of the security cell. IEEE 1149.1

and IEEE 1532 compliant USERCODE is supported.

Low Power and Power Management

The ispGAL22V10A family is designed with high speed low power design techniques to offer both high speed and

low power. With an advanced E

low power cell and no sense-ampliﬁers (full CMOS logic approach), the

ispGAL22V10A family offers fast pin-to-pin speeds, while simultaneously delivering low standby power without

requiring any “turbo bits” or other traditional power-management schemes.

I/O Conﬁguration

Each output supports a variety of output standards dependent on the V

CCO

. Outputs can also be conﬁgured for

open drain operation. Each input can be programmed to support a variety of standards, independent of the V

CCO

supplied to its I/O. For 28 PLCC package the V

CCO

and V

must be the same. The option to set the V

CCO

inde-

pendent of V

is available with the 32 QFN/QFNS package only. The I/O standards supported are:

• LVTTL

• LVCMOS 3.3

• LVCMOS 2.5

• LVCMOS 1.8

• 3.3V PCI Compatible

All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down

Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both

hardware and software is such that when the device is erased or if the user does not specify, the input structure is

conﬁgured to be a Pull-up Resistor.

Each ispGAL22V10A device I/O has an individually programmable output slew rate control bit. Each output can be

individually conﬁgured for fast slew or slow slew. The typical edge rate difference between fast and slow slew set-

ting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reﬂec-

tions, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the

fast slew rate can be used to achieve the highest speed.

IEEE 1149.1-Compliant Boundary Scan Testability

All ispGAL22V10A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows

functional testing of the circuit board on which the device is mounted through a serial scan path that can access all

critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto

test nodes, or test node data to be captured and shifted out for veriﬁcation. In addition, these devices can be linked

into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS

interface that corresponds to the power supply voltage.

IEEE 1532-Compliant In-System Programming

Programming devices in-system provides a number of signiﬁcant beneﬁts including rapid prototyping, lower inven-

tory levels, higher quality and the ability to make in-ﬁeld modiﬁcations. All ispGAL22V10A devices provide In-Sys-

tem Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been

implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE

1149.1 as the communication interface through which ISP is achieved, users get the beneﬁt of a standard, well-

deﬁned interface. All ispGAL22V10A devices are also compliant with the IEEE 1532 standard.

The ispGAL22V10A devices can be programmed across the commercial temperature and voltage range. The PC-

based Lattice software facilitates in-system programming of ispGAL22V10A devices. The software takes the

JEDEC ﬁle output produced by the design implementation software, along with information about the scan chain,

and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain

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器件捷径: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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