IS61C512
IS61C512
64K x 8 HIGH-SPEED CMOS STATIC RAM
ISSI
ISSI
®
®
JUNE 1997
FEATURES
•
•
•
•
•
•
•
•
Pin compatible with 128K x 8 devices
High-speed access time: 15, 20, 25, 35 ns
Low active power: 500 mW (typical)
Low standby power
— 250
µW
(typical) CMOS standby
Output Enable (
OE
) and two Chip Enable
(
CE1
and CE2) inputs for ease in applications
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V (±10%) power supply
DESCRIPTION
The
ISSI
IS61C512 is a very high-speed, low power, 65,536
word by 8-bit CMOS static RAMs. They are fabricated using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design tech-
niques, yields higher performance and low power consump-
tion devices.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down to 1 mW (typical) with CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (
WE
)
controls both writing and reading of the memory.
The IS61C512 is available in 32-pin 300-mil plastic DIP, SOJ
and TSOP (Type I) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
512 X 1024
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
SR024-1G
6/12/97
2-1
IS61C512
PIN CONFIGURATION
32-Pin DIP and SOJ
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
ISSI
PIN CONFIGURATION
32-Pin TSOP
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
NC
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
®
PIN DESCRIPTIONS
A0-A15
CE1
OE
WE
CE2
I/O0-I/O7
Vcc
GND
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
X
H
H
L
CE1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
D
OUT
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
SB
1
, I
SB
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–10 to +85
–65 to +150
1.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed
under ABSOLUTE MAXIMUM
RATINGS may cause permanent
damage to the device. This is a
stress rating only and functional
operation of the device at these or
any other conditions above those
indicated in the operational sec-
tions of this specification is not
implied. Exposure to absolute
maximum rating conditions for ex-
tended periods may affect reliabil-
ity.
2-2
Integrated Silicon Solution, Inc.
SR024-1G
6/12/97
IS61C512
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5V
±
10%
5V
±
10%
ISSI
®
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.3
–2
–2
Max.
—
0.4
V
CC
+ 0.5
0.8
2
2
Unit
V
V
V
V
µA
µA
Notes:
1. V
IL
= –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
I
CC
1
I
CC
2
I
SB
1
Parameter
Vcc Operating
Supply Current
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = 0
Com.
Ind.
-15 ns
Min. Max.
—
—
—
—
—
—
70
—
125
—
25
—
-20 ns
Min. Max.
—
—
—
—
—
—
70
90
115
135
25
30
-25 ns
Min. Max.
—
—
—
—
—
—
70
90
105
125
25
30
-35 ns
Min. Max.
—
—
—
—
—
—
70
90
90
115
25
30
Unit
mA
mA
mA
V
CC
= Max.,
Com.
I
OUT
= 0 mA, f = f
MAX
Ind.
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE1
≥
V
IH
or
CE2
≤
V
IL
, f = 0
Com.
Ind.
I
SB
2
CMOS Standby
Current (CMOS Inputs)
V
CC
= Max.,
Com.
CE1
≥
V
CC
– 0.2V,
Ind.
CE2
≤
0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
—
—
750
—
—
—
750
1
—
—
750
1
—
—
750
1
µA
mA
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
5
7
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc.
SR024-1G
6/12/97
2-3
IS61C512
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
-15 ns
Min. Max.
15
—
3
—
—
—
0
0
2
2
0
0
—
—
15
—
15
15
7
—
6
—
—
8
—
12
-20 ns
Min. Max.
20
—
3
—
—
—
0
0
3
3
0
0
—
—
20
—
20
20
8
—
9
—
—
9
—
18
-25 ns
Min. Max.
25
—
3
—
—
—
0
0
3
3
0
0
—
—
25
—
25
25
9
—
10
—
—
10
—
20
-35 ns
Min. Max.
35
—
3
—
—
—
0
0
3
3
0
0
—
—
35
—
35
35
12
—
12
—
—
12
—
20
ISSI
®
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
1
t
ACE
2
t
DOE
CE1
Access Time
CE2 Access Time
OE
Access Time
t
LZOE
(2)
OE
to Low-Z Output
t
HZOE
(2)
OE
to High-Z Output
t
LZCE
1
(2)
CE1
to Low-Z Output
t
LZCE
2
(2)
CE2 to Low-Z Output
t
HZCE
(2)
CE1
or CE2 to High-Z Output
t
PU
(3)
t
PD
(3)
CE1
or CE2 to Power-Up
CE1
or CE2 to Power-Down
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured
±500
mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
480
Ω
5V
5V
480
Ω
OUTPUT
30 pF
Including
jig and
scope
255
Ω
OUTPUT
5 pF
Including
jig and
scope
255
Ω
Figure 1a.
2-4
Figure 1b.
Integrated Silicon Solution, Inc.
SR024-1G
6/12/97
IS61C512
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
t
RC
ISSI
®
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
D
OUT
READ CYCLE NO. 2
(1,3)
t
RC
ADDRESS
t
AA
t
OHA
OE
t
DOE
t
HZOE
CE1
t
LZOE
t
ACE1/
t
ACE2
CE2
t
LZCE1/
t
LZCE2
t
HZCE
DATA VALID
HIGH-Z
D
OUT
HIGH-Z
t
PU
t
PD
50%
50%
ICC
SUPPLY
CURRENT
ISB
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE1
= V
IL
, CE2 = V
IH
.
3. Address is valid prior to or coincident with
CE1
LOW and CE2 HIGH transitions.
Integrated Silicon Solution, Inc.
SR024-1G
6/12/97
2-5
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