IS42SM81600E / IS42SM16800E / IS42SM32400E

IS42RM81600E / IS42RM16800E / IS42RM32400E

16Mx8, 8Mx16, 4Mx32

128Mb Mobile Synchronous DRAM

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access and pre-

charge

• Programmable CAS latency: 2, 3

• Programmable Burst Length: 1, 2, 4, 8, and Full

Page

• Programmable Burst Sequence:

• Sequential and Interleave

• Auto Refresh (CBR)

• TCSR (Temperature Compensated Self Refresh)

• PASR (Partial Arrays Self Refresh): 1/16, 1/8,

1/4, 1/2, and Full

• Deep Power Down Mode (DPD)

• Driver Strength Control (DS): 1/4, 1/2, and Full

• Configurations:

- 16M x 8

- 8M x 16

- 4M x 32

• Power Supply

IS42SMxxx – V

dd

/V

ddq

= 3.3 V

IS42RMxxx – V

dd

/V

ddq

= 2.5 V

• Packages:

x8 / x16 –TSOP II (54), BGA (54) [x16 only]

x32 – TSOP II (86), BGA (90)

• Temperature Range:

Commercial (0°C to +70°C)

Industrial (–40 ºC to 85 ºC)

• Die Revision: E

Advanced Information

AUGUST 2008

DESCRIPTION

ISSI's 128Mb Mobile Synchronous DRAM achieves high-

speed data transfer using pipeline architecture. All input

and output signals refer to the rising edge of the clock

input. Both write and read accesses to the SDRAM are

burst oriented. The 128Mb Mobile Synchronous DRAM

is designed to minimize current consumption making it

ideal for low-power applications. Both TSOP and BGA

packages are offered, including industrial grade products.

FEATURES

KEY TIMING PARAMETERS

Parameter

CLK Cycle Time

CAS

Latency = 3

CAS

Latency = 2

CLK Frequency

CAS

Latency = 3

CAS

Latency = 2

Access Time from CLK

CAS

Latency = 3

CAS

Latency = 2

5.0

6.5

5.4

6.5

5.4

6.5

—

5.4

ns

200

100

166

100

143

100

—

133

Mhz

5

10

6

10

7

10

—

7.5

ns

-5

1

-6

-7

-75E

Unit

OPTIONS

ADDRESSING TABLE

Parameter

Configuration

Refresh Count

Row Addressing

Column Addressing

Bank Addressing

Precharge Addressing

16M x 8

4M x 8 x 4 banks

4K/64ms

A0-A11

A0-A9

BA0, BA1

A10

8M x 16

2M x 16 x 4 banks

4K/64ms

A0-A11

A0-A8

BA0, BA1

A10

4M x 32

1M x 32 x 4 banks

4K/64ms

A0-A11

A0-A7

BA0, BA1

A10

out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain

the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

- www.issi.com

Rev. 00A

06/20/08

1

IS42SM81600E / IS42SM16800E / IS42SM32400E

IS42RM81600E / IS42RM16800E / IS42RM32400E

General Description

ISSI’s 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V – 2.5V

VDD and 3.3V – 2.5V VDDQ memory systems containing 134,271,728 bits. Internally configured as a quad-bank

DRAM with a synchronous interface. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving,

power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are

LVTTL (VDD = 3.3V) or LVCMOS (VDD = 2.5V) compatible. The 128Mb SDRAM has the ability to synchronously

burst data at a high data rate with automatic column-address generation, the ability to interleave between internal

banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during

burst access.

A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE

function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles

and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented

starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The

registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command

in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the

bank; A0-A11 (x8, x16 and x32) select the row). The READ or WRITE commands in conjunction with address bits

registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst

lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.

Functional Block Diagram (8Mx16)

CLK

CKE

CS

RAS

CAS

WE

DQML

DQMH

16

2

COMMAND

DECODER

&

CLOCK

GENERATOR

DATA IN

BUFFER

16

MODE

REGISTER

12

REFRESH

CONTROLLER

DQ 0-15

SELF

REFRESH

CONTROLLER

A10

A11

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

BA0

BA1

12

16

DATA OUT

BUFFER

V

DD

/V

DDQ

V

ss

/V

ss

Q

16

REFRESH

COUNTER

4096

ROW DECODER

MULTIPLEXER

12

MEMORY CELL

ARRAY

ROW

ADDRESS

LATCH

12

ROW

ADDRESS

BUFFER

BANK 0

SENSE AMP I/O GATE

COLUMN

ADDRESS LATCH

9

512

(x 16)

BANK CONTROL LOGIC

BURST COUNTER

COLUMN

ADDRESS BUFFER

COLUMN DECODER

9

2

Integrated Silicon Solution, Inc.

- www.issi.com

Rev. 00A

06/20/08

IS42SM81600E / IS42SM16800E / IS42SM32400E

IS42RM81600E / IS42RM16800E / IS42RM32400E

PIN CONFIGURATIONS

54 pin TSOP - Type II for x8

V

DD

DQ0

V

DD

Q

NC

DQ1

V

SS

Q

NC

DQ2

V

DD

Q

NC

DQ3

V

SS

Q

NC

V

DD

NC

WE

CAS

RAS

CS

BA0

BA1

A10

A0

A1

A2

A3

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

V

SS

DQ7

V

SS

Q

NC

DQ6

V

DD

Q

NC

DQ5

V

SS

Q

NC

DQ4

V

DD

Q

NC

V

SS

NC

DQM

CLK

CKE

NC

A11

A9

A8

A7

A6

A5

A4

V

SS

PIN DESCRIPTIONS: 16Mx8

A0-A11

A0-A9

BA0, BA1

DQ0 to DQ7

CLK

CKE

CS

RAS

CAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

WE

DQM

V

dd

Vss

V

ddq

Vss

q

NC

Write Enable

Data Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

Integrated Silicon Solution, Inc.

- www.issi.com

Rev. 00A

06/20/08

3

IS42SM81600E / IS42SM16800E / IS42SM32400E

IS42RM81600E / IS42RM16800E / IS42RM32400E

PIN CONFIGURATIONS

54 pin TSOP - Type II for x16

V

DD

DQ0

V

DD

Q

DQ1

DQ2

V

SS

Q

DQ3

DQ4

V

DD

Q

DQ5

DQ6

V

SS

Q

DQ7

V

DD

DQML

WE

CAS

RAS

CS

BA0

BA1

A10

A0

A1

A2

A3

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

V

SS

DQ15

V

SS

Q

DQ14

DQ13

V

DD

Q

DQ12

DQ11

V

SS

Q

DQ10

DQ9

V

DD

Q

DQ8

V

SS

NC

DQMH

CLK

CKE

NC

A11

A9

A8

A7

A6

A5

A4

V

SS

PIN DESCRIPTIONS: 8Mx16

A0-A11

A0-A8

BA0, BA1

DQ0 to DQ15

CLK

CKE

CS

RAS

CAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

WE

DQML

DQMH

V

dd

Vss

V

ddq

Vss

q

NC

Write Enable

x16 Lower Byte, Input/Output Mask

x16 Upper Byte, Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

4

Integrated Silicon Solution, Inc.

- www.issi.com

Rev. 00A

06/20/08

IS42SM81600E / IS42SM16800E / IS42SM32400E

IS42RM81600E / IS42RM16800E / IS42RM32400E

PIN CONFIGURATION

54-ball fBGA for x16

(Top View) (8.00 mm x 8.00 mm Body, 0.8 mm Ball Pitch)

PACKAGE CODE: B

1 2 3 4 5 6 7 8 9

A

B

C

D

E

F

G

H

J

VSS DQ15 VSSQ

DQ14 DQ13 VDDQ

DQ12 DQ11 VSSQ

DQ10 DQ9 VDDQ

DQ8

NC

VSS

CKE

A9

A6

A4

VDDQ DQ0 VDD

VSSQ DQ2 DQ1

VDDQ DQ4 DQ3

VSSQ DQ6 DQ5

VDD DQML DQ7

CAS

BA0

A0

A3

RAS

BA1

A1

A2

WE

CS

A10

VDD

DQMH CLK

NC

A8

VSS

A11

A7

A5

PIN DESCRIPTIONS: 8Mx16

A0-A11

A0-A8

BA0, BA1

DQ0 to DQ15

CLK

CKE

CS

RAS

CAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

WE

DQML

DQMH

V

dd

Vss

V

ddq

Vss

q

NC

Write Enable

x16 Lower Byte Input/Output Mask

x16 Upper Byte Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

Integrated Silicon Solution, Inc.

- www.issi.com

Rev. 00A

06/20/08

5

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	Integrated Silicon Solution ( ISSI )
零件包装代码	TSOP2
包装说明	TSOP2,
针数	54
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	5.4 ns
其他特性	AUTO/SELF REFRESH
JESD-30 代码	R-PDSO-G54
JESD-609代码	e3
长度	22.22 mm
内存密度	134217728 bit
内存集成电路类型	SYNCHRONOUS DRAM
内存宽度	8
湿度敏感等级	3
功能数量	1
端口数量	1
端子数量	54
字数	16777216 words
字数代码	16000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	16MX8
封装主体材料	PLASTIC/EPOXY
封装代码	TSOP2
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	260
认证状态	Not Qualified
座面最大高度	1.2 mm
自我刷新	YES
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Matte Tin (Sn) - annealed
端子形式	GULL WING
端子节距	0.8 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	10
宽度	10.16 mm
Base Number Matches	1

IS42SM81600E-75ETL

IS42SM81600E-75ETL概述

IS42SM81600E-75ETL规格参数

文档预览

推荐资源