INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4011B
gates
Quadruple 2-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Quadruple 2-input NAND gate
DESCRIPTION
The HEF4011B provides the positive quadruple 2-input
NAND function. The outputs are fully buffered for highest
noise immunity and pattern insensitivity of output
impedance.
HEF4011B
gates
Fig.2 Pinning diagram.
HEF4011BP(N):
HEF4011BD(F):
Fig.1 Functional diagram.
HEF4011BT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, I
DD
LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Quadruple 2-input NAND gate
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
I
n
→
O
n
Output transition times
HIGH to LOW
5
10
15
5
10
15
5
LOW to HIGH
10
15
t
TLH
t
THL
t
PHL
; t
PLH
SYMBOL
TYP
55
25
20
60
30
20
60
30
20
MAX
110
45
35
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
HEF4011B
gates
TYPICAL EXTRAPOLATION
FORMULA
28 ns
+
(0,55 ns/pF) C
L
14 ns
+
(0,23 ns/pF) C
L
12 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
1300 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
6000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
20 100 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
3
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