INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4006B
MSI
18-stage static shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
18-stage static shift register
DESCRIPTION
The HEF4006B is an 18-stage shift register arranged as
two 4-stage and two 5-stage shift registers with a common
clock input (CP). The two 4-stage shift registers each have
a data input (D
A
, D
B
) and a data output (O
3A
, O
3B
); the two
HEF4006B
MSI
5-stage shift registers each have a data input (D
C
, D
D
) and
data outputs from the fourth and fifth stages (O
3C
, O
4C
,
O
3D
, O
4D
).
The registers can be operated in parallel or interconnected
to form a single shift register of up to 18 bits. Data are
shifted into the first register position of each register from
the data inputs (D
A
to D
D
) and all the data in each register
are shifted one position to the right on the HIGH to LOW
transition of CP.
Fig.2 Pinning diagram.
HEF4006BP(N):
HEF4006BD(F):
HEF4006BT(D):
Fig.1 Functional diagram.
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
FUNCTION TABLE
D
n
D
1
X
Notes
1. X = state is immaterial
2.
3.
= positive-going transition
= negative-going transition
CP
O
n
(5)
D
1
no change
PINNING
D
A
to D
D
CP
data inputs
clock input
(HIGH to LOW; edge-triggered)
O
3A
to O
3D
; O
4C
; O
4D
data outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
4. D
1
= either HIGH or LOW
5. The moment D
1
appears at O depends on the register
length.
January 1995
2
Philips Semiconductors
Product specification
18-stage static shift register
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
CP
→
O
n
HIGH to LOW
5
10
15
5
LOW to HIGH
Output transition times
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
Minimum clock
pulse width; HIGH
Set-up time
D
n
→
CP
Hold time
D
n
→
CP
Maximum clock
pulse frequency
10
15
5
10
15
5
10
15
5
10
15
5
10
15
f
max
t
hold
t
su
t
WCPH
60
40
30
20
10
5
5
5
5
9
15
18
t
TLH
t
THL
t
PLH
t
PHL
90
40
30
90
40
35
60
30
20
60
30
20
30
20
15
10
5
0
−5
0
0
18
30
36
180
80
60
180
85
70
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
SYMBOL
MIN
TYP
MAX
HEF4006B
MSI
TYPICAL EXTRAPOLATION
FORMULA
63 ns
+
(0,55 ns/pF) C
L
29 ns
+
(0,23 ns/pF) C
L
22 ns
+
(0,16 ns/pF) C
L
63 ns
+
(0,55 ns/pF) C
L
29 ns
+
(0,23 ns/pF) C
L
27 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
see also waveforms Fig.4
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
600 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
3200 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
11 600 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
18-stage static shift register
HEF4006B
MSI
Fig.4
Waveforms showing minimum clock pulse width, and set-up and hold-times for D
n
to CP. Set-up and hold
times are shown as positive values but may be specified as negative values.
January 1995
5
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