Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
First-in First-out Dual Port Memory
16384 bits x 9 Organization
Fast Flag and Access Times: 15, 30 ns
Wide Temperature Range: -55°C to +125°C
Programmable Half Full Flag
Fully Expandable by Word Width or Depth
Asynchronous Read/Write Operations
Empty, Full and Half Flags in Single Device Mode
Retransmit Capability
Bi-directional Applications
Battery Back-up Operation: 2V Data Retention
TTL Compatible
Single 5V + 10% Power Supply
QML Q and V with SMD 5962-93177
ESSC B with Specification 9301/48
Description
The M672061H implements a first-in first-out algorithm, featuring asynchronous
read/write operations. The FULL and EMPTY flags prevent data overflow and under-
flow. The Expansion logic allows unlimited expansion in word size and depth with no
timing penalties. Twin address pointers automatically generate internal read and write
addresses, and no external address information are required for the Atmel FIFOs.
Address pointers are automatically incremented with the write pin and read pin. The 9
bits wide data are used in data communications applications where a parity bit for
error checking is necessary. The Retransmit pin resets the Read pointer to zero with-
out affecting the write pointer. This is very useful for retransmitting data when an error
is detected in the system.
Using an array of eight transistors (8T) memory cell, the M672061H combines an
extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 2 µW.
For military/space applications that demand superior levels of performance and reli-
ability the M672061H is processed according to the methods of the latest revision of
the MIL PRF 38535 (Q and V) or ESA SCC 9000.
Rad. Tolerant
High Speed
16 Kb x 9
Parallel FIFO with
Programmable
Flag
M672061H
4144H–AERO–03/04
1
Block Diagram
Pin Configuration
DIL ceramic 28-pin 300 mils
FP 28-pin 400 mils
2
M672061H
4144H–AERO–03/04
M672061H
Pin Description
Pin Name
I0 - 8
Q0 - 8
W
R
RS
EF
FF
XO/HF
XI
FL/RT
VCC
GND
Description
Inputs
Outputs
Write Enable
Read Enable
Reset
Empty Flag
Full Flag
Expansion Out/Half-Full Flag
Expansion IN
First Load/Retransmit
Power Supply
Ground
Data In (I
0
- I
8
)
Reset (RS)
Data inputs for 9-bit data
Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both
internal read and write pointers to the first location. A reset is required after power-up
before a write operation can be enabled. Both the Read Enable (R) and Write Enable
(W) inputs must be in the high state during the period shown in Figure 2 (i.e. t
RSS
before
the rising edge of RS) and should not change until tRSR after the rising edge of RS.
Otherwise, pulse write (or read) low during the reset operation loads the Programmable
Half Full Flag register from the data Inputs I0 - I8 (or data outputs Q0 - Q8) (shown in fig-
ure 2). In these two cases the Full Flag and the Programmable Half Full Flag are
reseted to high and the Empty Flag to low.
Figure 1.
Reset (no write to Programmable Half Full Flag register)
Notes:
1. EF, FF and HF may change status during reset, but flags will be valid at t
RSC
.
2. W and R = VIH around the rising edge of RS.
3
4144H–AERO–03/04
Figure 2.
Reset (write (read) to Programmable Half Full Flag register)
Write Enable (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.
Data set-up and hold times must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any
current read operation.
Once half the memory is filled, and during the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to low and remain in this state until the difference
between the write and read pointers is less than or equal to half of the total available
memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the
read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-
tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,
allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is
blocked from W, so that external changes to W will have no effect on the full FIFO stack.
Read Enable (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided that the
Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including
any current write operations. After Read Enable (R) goes high, the Data Outputs
(Q0 - Q8) will return to a high impedance state until the next Read operation. When all
the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the
“final” read cycle, but inhibiting further read operations while the data outputs remain in
a high impedance state. Once a valid write operation has been completed, the Empty
Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO
stack is empty, the internal read pointer is blocked from R, so that external changes to R
will have no effect on the empty FIFO stack.
This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to
ground to indicate that it is the first loaded (see Operating Modes). In the Single Device
Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-
necting the Expansion In (XI) to ground.
The M672061H can be set to retransmit data when the Retransmit Enable Control (RT)
input is pulsed low. A retransmit operation will set the internal read point to the first loca-
tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be
in the high state during retransmit. The retransmit feature is intended for use when a
number of writes are equal to or less than the depth of the FIFO has occured since the
last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (HF), in accordance with the relative locations of the
read and write pointers.
First Load/Retransmit
(FL/RT)
4
M672061H
4144H–AERO–03/04
M672061H
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an
operation in the single device mode. Expansion In (XI) is connected to Expansion Out
(XO) of the previous device in the Depth Expansion or Daisy Chain modes.
The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is
one location less than the read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.
The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer
is equal to the write pointer, indicating that the device is empty.
This is a dual-purpose output. In the single device mode, when Expansion In (XI) is con-
nected to ground, this output acts as an indication of a half-full memory.
The M672061H offers a variable offset for the Half Full condition. The offset is loaded
into a register during a reset cycle. When RS is low, the Programmable Half Full Flag
(PHF) can be loaded from the DATA inputs I
0
- I
8
by pulsing W low or from the DATA
outputs Q
0
- Q
8
by pulsing R low. The offset options are listed in table 1. If PHF is not
loaded during the reset cycle, the default offset will be the half of the total memory of the
device.
The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the
difference between the write and read pointers is less than or equal to the Programma-
ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half
of the total memory (if the Half Full register has not been loaded during the reset cycle).
After half the memory is filled and on the falling edge of the next write operation, the
Half-Full Flag (HF) will be set to low and will remain set until the difference between the
write and read pointers is less than or equal to half of the total memory of the device.
The Half-Full Flag (HF) is then reset by the rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of
the previous device. This output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device reaches the last memory
location.
Full Flag (FF)
Empty Flag (EF)
Expansion Out/Half-full
Flag (XO/HF)
Data Output (Q
0
- Q
8
)
DATA output for 9-bit wide data. This data is in a high impedance condition whenever
Read (R) is in a high state.
5
4144H–AERO–03/04
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
