Am29F004B
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
Am29F004B
Revision
E
Amendment
+1
Issue Date
Marech 28, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29F004B
4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
5.0 Volt single power supply operation
■
Top or bottom boot block configurations available
■
Minimum 1,000,000 write cycle guarantee per
sector
■
Package option
— Minimizes system-level power requirements
■
High performance
— Access times as fast as 55 ns
■
Manufactured on 0.32 µm process technology
■
Ultra low power consumption (typical values at
5 MHz)
— 32-pin PLCC
■
Compatible with JEDEC standards
— 20 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby mode current
■
Flexible sector architecture
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■
Embedded Algorithms
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■
20-year data retention at 125°C
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. This document contains information on a product under development at Advanced Micro De-
vices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
Publication#
22286
Rev:
E
Amendment/1
Issue Date:
March 28, 2005
A D V A N C E
I N F O R M A T I O N
internal algorithm that automatically preprograms the array (if it
is not already programmed) before executing the erase opera-
tion. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data# Polling), or
DQ6 (toggle)
status bits.
After a program or erase cycle is
completed, the device is ready to read array data or accept
another command.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during
power transitions.
The
hardware sector
protection feature dis-
ables
both program and erase operations in any combination
of sectors of memory. This can be achieved in-system or via
programming equipment.
The
Erase Suspend
feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any sector that is not selected for erasure. True back-
ground erase can thus be achieved.
The device offers a
standby mode
as a power-saving fea-
ture. Once the system places the device into the standby
mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via Fowler-
Nordheim tunnelling. The data is programmed using hot elec-
tron injection.
GENERAL DESCRIPTION
The Am29F004B is a 4 Mbit, 5.0 volt-only Flash memory
device organized as 524,288 bytes. The data appears on
DQ0–DQ7. The device is offered in a 32-pin PLCC package.
This device is designed to be programmed in-system with the
standard system 5.0 volt V
CC
supply. A 12.0 volt V
PP
is not
required for program or erase operations. The device can also
be programmed in standard EPROM programmers.
The device offers access times of 55, 70, 90, and 120 ns,
allowing high speed microprocessors to operate without wait
states. To eliminate bus contention each device has separate
chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
Each device requires only a
single 5.0 volt power supply
for
both read and write functions. Internally generated and regu-
lated voltages are provided for the program and erase
operations.
The Am29F004B is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands
are written to the command register using standard micropro-
cessor write timing. Register contents serve as inputs to an
internal state-machine that controls the erase and program-
ming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded Program
algorithm-an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command
sequence. This initiates the
Embedded Erase
algorithm–an
2
Am29F004B
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29F004B Device Bus Operations ................................10
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22
Figure 7. Maximum Negative Overshoot Waveform ...................... 22
Figure 8. Maximum Positive Overshoot Waveform ........................ 22
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Output Disable Mode .............................................................. 11
Table 2. Am29F004B Top Boot Block Sector
Addresses .......................................................................................11
Table 3. Am29F004B Bottom Boot Block Sector
Addresses .......................................................................................11
Table 4. Am29F004B Autoselect Codes (High Voltage Method) ....12
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
TTL/NMOS Compatible .......................................................... 23
CMOS Compatible .................................................................. 24
Figure 9. Test Setup ....................................................................... 25
Table 7. Test Specifications ........................................................... 25
Key to Switching Waveforms. . . . . . . . . . . . . . . . 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Operations .................................................................... 26
Figure 10. Read Operations Timings ............................................. 26
Erase/Program Operations ..................................................... 27
Figure 11. Program Operation Timings .......................................... 28
Figure 12. Chip/Sector Erase Operation Timings .......................... 28
Figure 13. Data# Polling Timings (During
Embedded Algorithms) ................................................................... 29
Figure 14. Toggle Bit Timings (During Embedded
Algorithms) ..................................................................................... 29
Figure 15. DQ2 vs. DQ6 ................................................................. 29
Figure 16. Sector Unlock Sequence Timing
Diagram .......................................................................................... 30
Figure 17. Sector Relock Timing Diagram ..................................... 30
Figure 18. Sector Protect/Unprotect Timing
Diagram .......................................................................................... 31
Sector Protection/Unprotection ............................................... 12
Figure 1. In-System Sector Protect/Sector Unprotect Algorithms ...13
Temporary Sector Unprotect .................................................. 14
Figure 2. Temporary Sector Unprotect Operation ...........................14
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data ................................................................ 15
Reset Command ..................................................................... 15
Autoselect Command Sequence ............................................ 15
Byte Program Command Sequence ....................................... 16
Figure 3. Program Operation ..........................................................16
Sector Erase Command Sequence ........................................ 16
Figure 4. Erase Operation ...............................................................17
Alternate CE# Controlled Erase/Program
Operations .............................................................................. 32
Figure 19. Alternate CE# Controlled Write
Operation Timings .......................................................................... 33
Erase Suspend/Erase Resume Commands ........................... 17
Table 5. Am29F004B Command Definitions ...................................18
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 19
DQ7: Data# Polling ................................................................. 19
Figure 5. Data# Polling Algorithm ...................................................19
DQ2: Toggle Bit II ................................................................... 20
Reading Toggle Bits DQ6/DQ2 .............................................. 20
DQ5: Exceeded Timing Limits ................................................ 20
DQ3: Sector Erase Timer ....................................................... 20
Figure 6. Toggle Bit Algorithm .........................................................21
Table 6. Write Operation Status ......................................................21
Erase and Programming Performance . . . . . . . 34
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 34
PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 34
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 35
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 35
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 36
Am29F004B
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