电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

74VCXH162244T

产品描述ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48
产品类别逻辑    逻辑   
文件大小74KB,共9页
制造商ST(意法半导体)
官网地址http://www.st.com/
下载文档 详细参数 全文预览

74VCXH162244T概述

ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48

74VCXH162244T规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称ST(意法半导体)
零件包装代码TSSOP
包装说明TSSOP-48
针数48
Reach Compliance Codenot_compliant
控制类型ENABLE LOW
系列ALVC/VCX/A
JESD-30 代码R-PDSO-G48
JESD-609代码e0
长度12.5 mm
负载电容(CL)30 pF
逻辑集成电路类型BUS DRIVER
最大I(ol)0.012 A
位数4
功能数量4
端口数量2
端子数量48
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE WITH SERIES RESISTOR
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP48,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)NOT SPECIFIED
电源3.3 V
Prop。Delay @ Nom-Sup3.4 ns
传播延迟(tpd)4.2 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.3 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度6.1 mm
Base Number Matches1

文档预览

下载PDF文档
®
74VCXH162244
LOW VOLTAGE CMOS 16-BIT BUFFER (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
s
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
t
PD
= 3.4 ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 3.8 ns (MAX.) at V
CC
= 2.3 to 2.7V
POWER-DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN) at V
CC
= 3.0V
|I
OH
| = I
OL
= 8 mA (MIN) at V
CC
= 2.3V
26Ω SERIE RESISTORS IN OUTPUTS
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.3V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16244
BUS HOLD PROVIDED ON DATA INPUTS
LATCH-UP PERFORMANCE EXCEEDS 300mA
ESD PERFORMANCE:
HBM >2000V; MM > 200V
T
(TSSOP48 Package)
ORDER CODES :
74VCXH162244T
PIN CONNECTION
DESCRIPTION
The 74VCXH162244 is a low voltage CMOS
16-BIT BUS BUFFER (INVERTED) fabricated
with sub-micron silicon gate and five layer metal
wiring C
2
MOS technology. It is ideal for low
power and very high speed 2.3 to 3.6V
applications; it can be interfaced to 3.6V signal
enviroment for both inputs and outputs.
Any nG control output governs four BUS
BUFFERS. Output Enable input (nG) tied
together gives full 16-bit operation.
When nG is LOW, the outputs are on. When nG
is HIGH, the output are in high impedance state.
This device is designed to be used with 3 state
memory address drivers, etc. Bus hold on data
inputs is provided in order to eliminate the need
for external pull-up or pull-down resistor.
The device circuits is including 26Ω series
resistance in the outputs. These resistors permit
to reduce line noise in high speed applications
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 1999
1/9

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1292  560  2119  2922  2349  16  47  11  28  49 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved