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GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls
August 1998
Revised January 2005
GTLP16T1655
16-Bit LVTTL/GTLP Universal Bus Transceiver
with High Drive GTLP and Individual Byte Controls
General Description
The GTLP16T1655 is a 16-bit universal bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface
between cards operating at LVTTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (
<
1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver Logic (GTL) JEDEC standard
JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Variable edge rate control pin to select desired edge rate
on the GTLP backplane (V
ERC
)
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
D-type flip-flop, latch and transparent data paths
s
A Port source/sink
−
24mA/
+
24mA
s
B Port sink
+
100mA
s
Partitioned as two 8-bit transceivers with individual latch
timing and output control but with a common clock
s
External pin to pre-condition I/O capacitance to high
state (V
CCBIAS
)
Ordering Code:
Order Number
GTLP16T1655MTD
Package Number
MTD64
Package Description
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS500172
www.fairchildsemi.com
GTLP16T1655
Connection Diagram
Pin Descriptions
Pin Names
1OEAB
2OEAB
1OEBA
2OEBA
OE
1LEAB
2LEAB
1LEBA
2LEBA
V
REF
CLK
1A1-1A8
2A1-2A8
1B1-1B8
2B1-2B8
B Port I/O Byte 1 and Byte 2
Description
A-to-B Output Enable (Active LOW)
Byte 1 and Byte 2
B-to-A Output Enable (Active LOW)
Byte 1 and Byte 2
Disables all I/O ports simultaneously
A-to-B Latch Enable (Transparent HIGH)
Byte 1 and Byte 2
B-to-A Latch Enable (Transparent HIGH)
Byte 1 and Byte 2
GTLP Reference Voltage
A-to-B and B-to-A Clock
A Port I/O Byte 1 and Byte 2
Truth Tables
(Note 1)
Inputs
OEAB
H
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
CLK
X
X
X
A
X
L
H
L
H
X
X
Output
B
Z
L
H
L
H
B
0
(Note 2)
B
0
(Note 3)
High Impedance
Transparent
Transparent
Registered
Registered
Previous State
Previous State
Mode
↑
↑
H
L
Inputs
OE
L
L
L
L
H
OEAB
(Note 4)
L
L
H
H
X
OEBA
(Note 4)
L
H
L
H
X
Outputs
A Port
Active
Z
Active
Z
Z
B Port
Active
Active
Z
Z
Z
Inputs
V
ERC
V
CC
GND
Output Edge
B Port
Slow
Fast
Note 1:
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLK.
Note 2:
Output level before the indicated steady state input conditions were established, provided CLK was HIGH prior to LEAB going LOW.
Note 3:
Output level before the indicated steady state input conditions were established.
Note 4:
OEAB and OEBA are byte-wide enables. Each is proceeded by a number indicating the byte controlled.
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2
GTLP16T1655
Functional Description
The GTLP16T1655 is a high drive (100 mA) 16-bit univer-
sal bus transceiver containing D-type flip-flop, latch and
transparent modes of operation for the data path. The
device is uniquely partitioned as two 8-bit transceivers with
individual latch timing and output control signals but with a
common clock pin (CLK) for both transceiver words. Data
flow for each word is determined by the respective latch
enables (xLEAB and xLEBA), output enables (xOEAB and
xOEBA) and clock (CLK). The output enables (1OEAB,
1OEBA, and 2OEAB and 2OEBA) control Byte1 and Byte2
data for the A to B and B to A directions respectively.
For A-to-B data flow, the devices operate in the transparent
mode when LEAB is HIGH. When LEAB transitions LOW,
the A data is latched independent of CLK HIGH or LOW. If
LEAB is LOW the A data is registered on the CLK
LOW-to-HIGH transition. When OEAB is LOW the outputs
are active. With OEAB HIGH the outputs are HIGH imped-
ance. Data flow for the B-to-A direction is identical but uses
OEBA, LEBA and CLK. Note that CLK is common to both
directions and both 8-bit words. OE is also common and is
used to disable all I/O ports simultaneously.
Logic Diagrams
3
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GTLP16T1655
Absolute Maximum Ratings
(Note 5)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
DC Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 6)
DC Output Sink Current into
A Port I
OL
DC Output Source Current from
A Port I
OH
DC Output Sink Current
into B Port in the LOW State,
I
OL
(Note 7)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
V
O
>
V
CC
ESD Rating
Storage Temperature (T
STG
)
200 mA
48 mA
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
Recommended Operating
Conditions
Supply Voltage V
CC
Bus Termination Voltage (V
TT
)
GTLP
GTL
V
REF
GTLP
GTL
Input Voltage (V
I
)
on A Port and Control Pins
on B Port
HIGH Level Output Current (I
OH
)
A Port
0.0V to V
CC
0.0V to V
tt
0.87V to 1.1V
0.74V to 0.87V
1.35V to 1.65V
1.14V to 1.26V
3.0V to 3.6V
−
48 mA
−
24 mA
+
24mA
+
100 mA
−
40
°
C to
+
85
°
C
−
50 mA
−
50 mA
+
50 mA
>
2000V
−
65
°
C to
+
150
°
C
LOW Level Output Current (I
OL
)
A Port
B Port
Operating Temperature (T
A
)
Note 5:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 6:
I
O
Absolute Maximum Rating must be observed.
Note 7:
V
TT
and R
term
can be adjusted to accommodate backplane imped-
ances other than 50Ω, within the boundaries of not exceeding the DC
Absolute I
OL
ratings (200 mA). Similarly V
REF
can be adjusted to compen-
sate for changes in V
TT
.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
REF
=
1.0V (unless otherwise noted).
Symbol
V
IH
V
IL
V
REF
V
IK
V
OH
A Port
B Port
Others
B Port
Others
GTLP
V
CC
=
3.0V
V
CC
=
Min to Max (Note 9)
V
CC
=
3.0V
V
OL
A Port
V
CC
=
Min to Max (Note 9)
V
CC
=
3.0V
B Port
V
CC
=
3.0V
I
I
= −18
mA
I
OH
= −100 µA
I
OH
= −12
mA
I
OH
= −24
mA
I
OL
=
100
µA
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
40 mA
I
OL
=
80 mA
I
OL
=
100 mA
I
I
A Port
B Port
I
OFF
I
I(hold)
Except
V
ERC
A Port
V
CC
=
3.0V
V
CC
=
3.6V
V
CC
=
3.6V
V
CC
=
3.6V
V
CC
=
0
V
I
=
V
CC
or 0V
V
I
=
V
CC
or 0V
V
I
=
V
TT
or GND
V
I
or V
O
=
0 to
V
CC
V
I
=
0.8V
V
I
=
2.0V
V
I
=
0 to V
CC
75
−75
±500
µA
Control Pins V
CC
=
3.6V
V
CC
−0.2
2.4
2.2
0.20
0.40
0.50
0.20
0.40
0.50
±10
±10
±10
100
µA
µA
µA
µA
V
V
V
0.74
1.0
Test Conditions
Min
V
REF
+0.05
2.0
0.0
V
REF
−0.05
0.8
1.1
−1.2
Typ
(Note 8)
V
TT
V
V
V
V
V
V
Max
Units
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4
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