IS61LV6432
IS61LV6432
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
ISSI
MAY 1998
®
ISSI
®
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• 3.3V V
CC
and 2.5V V
CCQ
for 2.5 I/O's
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
Q
or V
CCQ
to alter their power-up state
• Industrial temperature available
DESCRIPTION
The
ISSI
IS61LV6432 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 65,536
words by 32 bits, fabricated with
ISSI
's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ1-DQ8,
BW2
controls DQ9-DQ16,
BW3
controls DQ17-DQ24,
BW4
controls DQ25-DQ32, conditioned
by
BWE
being LOW. A LOW on
GW
input would cause all bytes
to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter-
nally by the IS61LV6432 and controlled by the
ADV
(burst
address advance) input pin.
Asynchronous signals include output enable (
OE
), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
Q
, on MODE pin selects LINEAR Burst. A V
CCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
—
Parameter
CLK Access Time
Cycle Time
Frequency
-166
5
6
166
-133
5
7.5
133
-117
5
8.5
117
-5
5
10
100
-6
6
12
83
-7
7
13
75
-8
8
15
66
Unit
ns
ns
MHz
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.
We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
PRELIMINARY
SR018-1C
06/01/98
1
IS61LV6432
BLOCK DIAGRAM
MODE
Q0
A0'
ISSI
®
CLK
CLK
A0
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1'
A1
64K x 32
MEMORY
ARRAY
14
16
A15-A0
16
D
Q
ADDRESS
REGISTER
CE
CLK
32
32
GW
BWE
BW4
D
Q
DQ32-DQ25
BYTE WRITE
REGISTERS
CLK
D
Q
BW3
DQ24-DQ17
BYTE WRITE
REGISTERS
CLK
D
Q
BW2
DQ16-DQ9
BYTE WRITE
REGISTERS
CLK
D
Q
BW1
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
CE1
CE2
D
Q
4
CE3
ENABLE
REGISTER
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
32
DATA[32:1]
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc.
PRELIMINARY
SR018-1C
06/01/98
IS61LV6432
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
VCC
GND
CLK
CE2
A6
A7
ISSI
®
GW
BWE
OE
ADSC
ADSP
ADV
BW4
BW3
BW2
BW1
CE3
CE1
NC
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
VCCQ
VCC
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8
A9
NC
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
NC
PIN DESCRIPTIONS
A0-A15
CLK
Address Inputs
Clock
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
Global Write Enable
Synchronous Chip Enable
Output Enable
GND
Q
NC
DQ1-DQ32
ZZ
MODE
V
CC
GND
V
CCQ
Data Input/Output
Sleep Mode
Burst Sequence Mode
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V
Isolated Output Buffer Ground
No Connect
ADSP
ADSC
ADV
BW1
-
BW4
BWE
GW
CE1
, CE2,
CE3
OE
Integrated Silicon Solution, Inc.
PRELIMINARY
SR018-1C
06/01/98
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
NC
3
IS61LV6432
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
ISSI
CE1
H
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
®
CE3 ADSP ADSC ADV WRITE
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE
=L means any one or more byte write enable signals (
BW
1-
BW
4) and
BWE
are LOW or
GW
is LOW.
WRITE
=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
GW
H
H
H
X
L
BWE
H
X
L
L
X
BW1
X
H
L
L
X
BW2
X
H
H
L
X
BW3 BW4
X
H
H
L
X
X
H
H
L
X
4
Integrated Silicon Solution, Inc.
PRELIMINARY
SR018-1C
06/01/98
IS61LV6432
INTERLEAVED BURST ADDRESS TABLE (MODE = V
CCQ
or No Connect)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
ISSI
®
LINEAR BURST ADDRESS TABLE (MODE = GND
Q
)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
T
BIAS
T
STG
P
D
I
OUT
V
IN
, V
OUT
V
IN
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
Value
Unit
–10 to +85
°C
–55 to +150
°C
1.8
W
100
mA
–0.5 to V
CCQ
+ 0.3
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc.
PRELIMINARY
SR018-1C
06/01/98
5
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