74AC299 • 74ACT299 8-Input Universal Shift/Storage Register
July 1988
Revised March 2005
74AC299 • 74ACT299
8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The AC/ACT299 is an 8-bit universal shift/storage register
with 3-STATE outputs. Four modes of operation are possi-
ble: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional out-
puts are provided for flip-flops Q
0
, Q
7
to allow easy serial
cascading. A separate active LOW Master Reset is used to
reset the register.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Common parallel I/O for reduced pin count
s
Additional serial inputs and outputs for expansion
s
Four operating modes: shift left, shift right, load
and store
s
3-STATE outputs for bus-oriented applications
s
Outputs source/sink 24 mA
s
ACT299 has TTL-compatible inputs
Ordering Code:
Order Number
74AC299SC
74AC299SCX_NL
(Note 1)
74AC299SJ
74AC299MTC
74AC299PC
74ACT299SC
74ACT299MTC
74ACT299PC
Package Number
M20B
M20B
M20D
MTC20
N20A
M20B
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
CP
DS
0
DS
7
S
0
, S
1
MR
OE
1
, OE
2
I/O
0
–I/O
7
Q
0
, Q
7
Description
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
3-STATE Output Enable Inputs
Parallel Data Inputs or
3-STATE Parallel Outputs
Serial Outputs
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009893
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74AC299 • 74ACT299
Logic Symbols
Truth Table
Inputs
MR S
1
L
H
H
H
H
X
H
L
H
L
S
0
X
H
H
L
L
CP
Response
X
X
Asynchronous Reset; Q
0
–Q
7
Parallel Load; I/O
n
o
Q
n
LOW
Shift Right; DS
0
o
Q
0
, Q
0
o
Q
1
, etc.
Shift Left, DS
7
o
Q
7
, Q
7
o
Q
6
, etc.
Hold
IEEE/IEC
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
LOW-to-HIGH Transition
Functional Description
The AC/ACT299 contains eight edge-triggered D-type flip-
flops and the interstage logic necessary to perform syn-
chronous shift left, shift right, parallel load and hold opera-
tions. The type of operation is determined by S
0
and S
1
, as
shown in the Truth Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
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2
74AC299 • 74ACT299
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74AC299 • 74ACT299
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
(Unless Otherwise Specified)
AC
ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (
'
V/
'
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. Obviously the databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of FACT
¥
circuits outside databook specifi-
cations.
0.5V
V
CC
0.5V
2.0V to 6.0V
4.5V to 5.0V
0V to V
CC
0V to V
CC
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
20 mA
20 mA
V
O
DC Output Voltage (V
O
)
0.5V to V
CC
0.5V
r
50 mA
DC Output Source or Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
(PDIP)
140
q
C
0.5V
V
CC
0.5V
40
q
C to
85
q
C
r
50 mA
65
q
C to
150
q
C
125 mV/ns
DC Electrical Characteristics for AC
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 5)
I
OLD
I
OHD
I
CC
(Note 5)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
5.5
4.0
5.5
5.5
0.002
0.001
0.001
T
A
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
Guaranteed Limits
Units
V
OUT
V
Conditions
0.1V
or V
CC
0.1V
V
OUT
0.1V
V
or V
CC
0.1V
V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
I
OH
I
OH
I
OH
12 mA
24 mA
24 mA (Note 3)
50
P
A
V
IL
or V
IH
12 mA
24 mA
24 mA (Note 3)
V
CC
, GND
1.65V Max
3.85V Min
V
CC
or GND
V
I
OUT
V
IN
0.44
0.44
0.44
V
I
OH
I
OH
I
OH
V
I
r
0.1
r
1.0
86
P
A
mA
mA
V
OLD
V
OHD
V
IN
75
40.0
P
A
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4
74AC299 • 74ACT299
DC Electrical Characteristics for AC
Symbol
I
OZT
Parameter
Maximum I/O Leakage Current
V
CC
(V)
5.5
T
A
Typ
(Continued)
25
q
C
T
A
40
q
C to
85
q
C
r
3.0
Units
Conditions
V
I
(OE)
V
I
V
O
V
IL
, V
IH
Guaranteed Limits
r
0.3
P
A
V
CC
, GND
V
CC
, GND
Note 3:
All outputs loaded; threshold on input associated with output under test.
Note 4:
Maximum test duration 20 ms, one output loaded at a time.
Note 5:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
DC Electrical Characteristics for ACT
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
V
CC
(V)
4.5
5.5
3.0
4.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
CCT
I
OLD
I
OHD
I
CC
I
OZT
Maximum Input Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent Supply Current
Maximum I/O
Leakage Current
5.5
5.5
5.5
5.5
5.5
5.5
4.0
0.6
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
0.0001
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
V
I
OH
I
OH
24 mA
24 mA (Note 6)
50
P
A
V
IL
or V
IH
V
I
OUT
V
IN
V
I
OL
24 mA
I
OL
24 mA (Note 6)
V
I
V
I
V
CC
, GND
V
CC
2.1V
1.65V Max
3.85V Min
V
CC
or GND
V
IL
, V
IH
V
CC
, GND
V
CC
, GND
r
0.1
r
1.0
1.5
75
P
A
mA
mA
mA
V
OLD
V
OHD
V
IN
V
I
V
O
V
I
(OE)
75
40.0
P
A
P
A
r
0.3
r
3.0
Note 6:
All outputs loaded; thresholds on input associated with output under test.
Note 7:
Maximum test duration 2.0 ms, one output loaded at a time.
5
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