IDT74LVC1G132A
3.3V CMOS SINGLE POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS SINGLE
POSITIVE-NAND GATE WITH
SCHMITT-TRIGGER INPUTS
AND 5 VOLT TOLERANT I/O
FEATURES:
–
–
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.65mm pitch PSOP package
Extended commercial range of – 40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 1.65V to 3.6V, Extended Range
V
CC
= 2.5V ±0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVC1G132A
ADVANCE
INFORMATION
DESCRIPTION:
This single positive NAND gate is built using advanced dual metal CMOS
technology. The LVC1G132A is designed for 1.65V to 3.6V V
CC
operation
and performs the Boolean function Y = A · B or Y =
A
+
B
in positive logic.
These circuits are temperature compensated and can be triggered from
the slowest of input ramps and still give clean jitter-free output signals.
Drive Features for LVC1G132A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
A
PIN CONFIGURATION
1
2 SO5-1
3
4
Y
5
A
Y
B
V
CC
B
GND
PSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
A, B
Y
Description
Data Inputs
Data Output
FUNCTION TABLE
Inputs
A
H
L
X
B
H
X
L
(1)
Output
Y
L
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4933/-
IDT74LVC1G132A
3.3V CMOS SINGLE POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
(1)
Unit
V
°C
mA
mA
mA
LVC 1G Link
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
–0.5 to +6.5
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
LVC 1G Link
– 65 to +150
– 50 to +50
– 50
±100
NOTE:
1. As applicable to the device type.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C To +85°C
Symbol
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
Test Conditions
V
I
= 0 to 5.5V
V
I
= 0 to 5.5V
Min.
—
—
—
—
—
—
—
Typ.
(1)
—
—
– 0.7
100
—
—
—
Max.
±5
±10
– 1.2
—
10
10
500
µA
Unit
µA
µA
V
mV
µA
V
IN
= GND or V
CC
3.6
<
Vin
<
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies to 3-state outputs in the disabled state only.
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVC1G132A
3.3V CMOS SINGLE POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 1.65V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 12mA
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 12mA
I
OL
= 24mA
Min.
V
CC
– 0.2
1.2
1.7
2.2
2.4
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.45
0.7
0.4
0.55
LVC 1G Link
Unit
V
V
CC
= 1.65V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 1.65V to 3.6V
V
CC
= 1.65V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
HYSTERESIS CHARACTERISTICS
Parameter
V
T+
Positive-going
threshold
Test Conditions
Input Voltage, from V
IL
to V
IH
, in a linear ramp observing the output
transition.
V
CC
1.65V
2.3V
2.7V
3V
3.6V
1.65V
2.3V
2.7V
3V
3.6V
1.65V
2.3V
2.7V
3V
3.6V
Min.
—
—
0.8‡
0.8‡
0.8‡
—
—
0.4
0.6
0.8
—
—
0.3
0.3
0.3
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
—
2
2
2
—
—
1.4‡
1.5‡
1.8‡
—
—
1.1
1.2
1.2
Unit
V
V
T–
Negative-going
threshold
Input Voltage, from V
IH
to V
IL
, in a linear ramp observing the output
transition.
V
∆V
T
Hysteresis
(V
T+
– V
T–
)
∆V
T min =
|
V
T+ min
– V
T– max
|
∆V
T max =
|
V
T+ max
– V
T– min
|
V
‡ = Guaranteed by design.
OPERATING CHARACTERISTICS, TA = 25oC
V
CC
= 1.8V±0.15V
Symbol
C
PD
Parameter
Power Dissipation Capacitance
Test Conditions
C
L
= 0pF, f = 10Mhz
(1)
V
CC
= 2.5V±0.2V
Min.
1
Max.
7.9
V
CC
= 2.7V
Min.
—
Max.
7.5
V
CC
= 3.3V±0.3V
Min.
1
Max.
6.4
Unit
ns
Typical
—
V
CC
= 2.5V±0.2V
Typical
—
V
CC
= 3.3V±0.3V
Typical
—
Unit
pF
SWITCHING CHARACTERISTICS
Symbol
Parameter
t
PLH
Propagation Delay
A or B to Y
t
PHL
Min.
1
V
CC
= 1.8V±0.15V
Max.
13.7
NOTE:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
3
IDT74LVC1G132A
3.3V CMOS SINGLE POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
6
2.7
1.5
300
300
50
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
V
CC
(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
LVC 1G Link
V
CC
(1)
= 2.7V
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC 1G Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SW ITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL +
V
LZ
V
OL
V
OH
V
OH -
V
LZ
0V
LVC 1G Link
V
LOAD
Open
GND
V
IN
D.U.T.
V
OUT
R
T
500
Ω
C
L
LVC 1G Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC 1G Link
t
SU
t
H
GND
Open
LVC 1G Link
t
REM
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
PULSE WIDTH
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
LVC 1G Link
t
H
V
T
4
IDT74LVC1G132A
3.3V CMOS SINGLE POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
1.8V ± 0.15V TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 1.8V ± 0.15V
2 x Vcc
Vcc
V
CC
/ 2
150
150
30
Unit
V
V
V
mV
mV
pF
LVC 1G Link
PROPAGATION DELAY
SAM E PHASE
INPUT TRANSITIO N
t
PLH
O U TPU T
t
PLH
O PPO SITE PHASE
INPUT TRANSITIO N
t
PHL
V
IH
V
T
0V
LVC 1G Link
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
V
LOAD
O pen
1000
Ω
Pulse
G enerato r
R
T
(1)
ENABLE AND DISABLE TIMES
ENABLE
C O N TRO L
INPUT
t
PZL
O UTPU T
SW ITCH
NO R M ALLY
CLOSE D
LO W
t
PZH
O U TPU T
SW ITCH
N O RM ALLY
OPEN
H IG H
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL +
V
LZ
V
OL
V
OH
V
OH –
V
HZ
0V
GND
V
IN
D.U.T.
V
OUT
C
L
1000
Ω
LVC 1G Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTE:
LVC 1G Link
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTE:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC 1G Link
DATA
INPUT
TIM ING
INPUT
t
SU
t
H
GND
Open
LVC 1G Link
t
REM
ASYNCHRONOUS
C O N TR OL
SYN CHRONOUS
C O N TR OL
PULSE WIDTH
t
SU
t
H
LO W -H IG H -LO W
PULSE
t
W
HIG H-LOW -HIG H
PULSE
V
T
V
T
LVC 1G Link
5
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