3-Volt Advanced Boot Block Flash
Memory
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Preliminary Datasheet
Product Features
•
Flexible SmartVoltage Technology
— 2.7 V–3.6 V Read/Program/Erase
— 12 V V
PP
Fast Production Programming
•
Intel
®
Flash Data Integrator Software
— Flash Memory Manager
— System Interrupt Manager
— Supports Parameter Storage, Streaming
Data (e.g., Voice)
•
1.65 V–2.5 V or 2.7 V–3.6 V I/O Option
— Reduces Overall System Power
•
High Performance
— 2.7 V–3.6 V: 70 ns Max Access Time
•
Extended Cycling Capability
— Minimum 100,000 Block Erase Cycles
Guaranteed
•
Optimized Block Sizes
— Eight 8-KB Blocks for Data,Top or
Bottom Locations
— Up to One Hundred Twenty-Seven 64-
KB Blocks for Code
•
Automatic Power Savings Feature
— Typical I
CCS
after Bus Inactivity
•
Standard Surface Mount Packaging
— 48-Ball CSP Packages
— 40- and 48-Lead TSOP Packages
•
Block Locking
— V
CC
-Level Control through WP#
•
Density and Footprint Upgradeable for
common package
— 4-, 8-, 16-, 32- and 64-Mbit Densities
•
Low Power Consumption
— 9 mA Typical Read Current
•
Absolute Hardware-Protection
— V
PP
= GND Option
— V
CC
Lockout Voltage
•
ETOX™ VIII (0.13
µm)
Flash
Technology
— 32- and 64-Mbit Densities
•
Extended Temperature Operation
— –40 °C to +85 °C
•
ETOX™ VII (0.18
µm)
Flash Technology
— 16-, 32- and 64-Mbit Densities
•
Automated Program and Block Erase
— Status Registers
•
ETOX ™ VI (0.25µm) Flash Technology
— 8-, 16-, and 32-Mbit Densities
•
ETOX™ V (0.4µm)Flash Technologies
— 4-Mbit Density
•
x8 not recommended for new designs
•
4-Mbit density not recommended for new
designs
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290580-013
October 2001
The Intel
®
3-Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.13
µm
and 0.18
µm
technologies, represent a feature-rich solution at overall lower system cost. The 3-
Volt Advanced Boot Block Flash Memory products in x16 will be available in 48-lead TSOP and
48-ball CSP packages. The x8 option of this product family will be available only in 40-lead
TSOP and 48-ball µBGA* packages. Additional information on this product family can be
obtained by accessing Intel’s website at: http://www.intel.com/design/flash.
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://developer.intel.com/design/flash.
Copyright © Intel Corporation 1999– 2001.
*Other names and brands may be claimed as the property of others.
Preliminary
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Contents
1.0
2.0
Introduction
.................................................................................................................. 1
1.1
Product Overview .................................................................................................. 2
Product Description
.................................................................................................. 3
2.1
2.2
Package Pinouts ...................................................................................................3
Block Organization .............................................................................................. 10
2.2.1 Parameter Blocks ................................................................................... 10
2.2.2 Main Blocks ............................................................................................10
3.0
Principles of Operation
..........................................................................................10
3.1
Bus Operation ..................................................................................................... 10
3.1.1 Read ....................................................................................................... 11
3.1.2 Output Disable........................................................................................ 11
3.1.3 Standby .................................................................................................. 11
3.1.4 Deep Power-Down / Reset ..................................................................... 11
3.1.5 Write ....................................................................................................... 12
Modes of Operation............................................................................................. 12
3.2.1 Read Array ............................................................................................. 12
3.2.2 Read Identifier ........................................................................................ 14
3.2.3 Read Status Register ............................................................................. 14
3.2.4 Program Mode........................................................................................ 15
3.2.5 Erase Mode ............................................................................................15
Block Locking ...................................................................................................... 17
3.3.1 WP# = V
IL
for Block Locking ..................................................................17
3.3.2 WP# = V
IH
for Block Unlocking .............................................................. 18
V
PP
Program and Erase Voltages .......................................................................18
3.4.1 V
PP
= V
IL
for Complete Protection ......................................................... 18
Power Consumption ............................................................................................18
3.5.1 Active Power ..........................................................................................19
3.5.2 Automatic Power Savings (APS) ............................................................ 19
3.5.3 Standby Power ....................................................................................... 19
3.5.4 Deep Power-Down Mode .......................................................................19
Power-Up/Down Operation ................................................................................. 19
3.6.1 RP# Connected to System Reset...........................................................20
3.6.2 V
CC
, V
PP
and RP# Transitions ............................................................... 20
Power Supply Decoupling ................................................................................... 20
3.2
3.3
3.4
3.5
3.6
3.7
4.0
Electrical Specifications
........................................................................................ 21
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Absolute Maximum Ratings................................................................................. 21
Operating Conditions........................................................................................... 22
Capacitance ........................................................................................................22
DC Characteristics .............................................................................................. 23
AC Characteristics —Read Operations............................................................... 26
AC Characteristics —Write Operations ............................................................... 30
Program and Erase Timings................................................................................ 34
Preliminary
iii
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
5.0
6.0
7.0
A
B
C
D
E
Reset Operations
..................................................................................................... 36
Ordering Information
.............................................................................................. 37
Additional Information
........................................................................................... 39
Write State Machine Current/Next States
................................................. 40
Architecture Block Diagram
........................................................................... 41
Word-Wide Memory Map Diagrams
............................................................. 42
Byte-Wide Memory Map Diagrams
.............................................................. 48
Program and Erase Flowcharts
.................................................................... 51
iv
Preliminary
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Number
-001
Original version
Section 3.4,
V
PP
Program and Erase Voltages,
added
Updated Figure 9:
Automated Block Erase Flowchart
Updated Figure 10:
Erase Suspend/Resume Flowchart
(added program to table)
Updated Figure 16:
AC Waveform: Program and Erase Operations
(updated notes)
I
PPR
maximum specification change from ±25
µA
to ±50
µA
Program and Erase Suspend Latency specification change
Updated Appendix A:
Ordering Information
(included 8 M and 4 M information)
Updated Figure, Appendix D:
Architecture Block Diagram
(Block info. in words not bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V V
PP
read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved
Ordering Information
from Appendix to Section 6.0; updated information
Moved
Additional Information
from Appendix to Section 7.0
Updated figure Appendix B,
Access Time vs. Capacitive Load
Updated figure Appendix C,
Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated
Program Flowchart
Updated
Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A
1
–A
20
= 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
V
CC
and V
CCQ
absolute maximum specification = 3.7 V (Section 4.1)
Combined I
PPW
and I
CCW
into one specification (Section 4.4)
Combined I
PPE
and I
CCE
into one specification (Section 4.4)
Max Parameter Block Erase Time (t
WHQV2
/t
EHQV2
) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (t
WHQV3
/t
EHQV3
) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (t
WHRH2
/t
EHRH2
) changed to 5 µs typical and 20 µs maximum
(Section 4.7)
Ordering Information
updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA
package diagrams corrected (Figures 3 and 4)
I
PPD
test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA
package top side mark information added (Section 6)
V
IH
and V
IL
Specification change (Section 4.4)
I
CCS
test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Datasheet renamed from
Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
Corrected RP# pin description in Table 2,
3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in
Ordering Information
Description
-002
-003
-004
-005
-006
-007
Preliminary
v
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
