DRAM
MT4C4001J
1 MEG x 4 DRAM
Fast Page Mode DRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
DQ1
DQ2
WE\
RAS\
A9
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
PIN ASSIGNMENT
(Top View)
20-Pin DIP (C, CN)
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\ (CBR),
and HIDDEN
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
20
19
18
17
16
15
14
13
12
11
Vss
DQ4
DQ3
CAS\
OE\
A8
A7
A6
A5
A4
20-Pin SOJ (ECJ,ECJA),
20-Pin LCC (ECN), &
20-Pin Gull Wing (ECG)
DQ1
DQ2
WE\
RAS\
A9
1
2
3
4
5
26
25
24
23
22
Vss
DQ4
DQ3
CAS\
OE\
20-Pin DIP (CZ)
OE\
DQ3
Vss
DQ2
RAS\
A0
A2
Vcc
A5
A7
1
3
5
7
9
11
13
15
17
19
2
4
6
CAS\
DQ4
DQ1
A0
A1
A2
A3
Vcc
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
8 WE\
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
OPTIONS
• Timing
70ns access
80ns access
100ns access
120ns access
MARKING
-7
-8
-10
-12
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state memory
containing 4,194,304 bits organized in a x4 configuration. Dur-
• Packages
ing READ or WRITE cycles each bit is uniquely addressed
Ceramic DIP (300 mil)
CN
No. 103
through the 20 address bits which are entered 10 bits (A0-
Ceramic DIP (400 mil)
C
No. 104
A9) at a time. RAS\ is used to latch the
fi
rst 10 bits and CAS\
Ceramic LCC*
ECN
No. 202
the later 10 bits. A READ or WRITE cycle is selected with
Ceramic ZIP
CZ
No. 400
the WE\ input. A logic HIGH on WE\ dictates READ mode
Ceramic SOJ
ECJ
No. 504
while a logic LOW on WE\ dictates WRITE mode. During a
Ceramic SOJ w/ Cu J-lead
ECJA No. 504A
WRITE cycle, data-in (D) is latched by the falling edge of WE\
Ceramic Gull Wing
ECG
No. 600
or CAS\, whichever occurs last. If WE\ goes LOW prior to
CAS\ going LOW, the output pin(s) remain open (High-Z) until
*NOTE:
If solder-dip and lead-attach is desired on LCC pack-
the next CAS\ cycle. If WE\ goes LOW after data reaches the
ages, lead-attach must be done prior to the solder-dip opera-
output pin(s), Qs are activated and retain the selected cell data
tion.
as long as CAS\ remains low (regardless of WE\ or RAS\).
This LATE WE\ pulse results in a READ-WRITE cycle. The
four data inputs and four data outputs are routed through four
For more products and information
pins using common I/O and pin direction is controlled by WE\
please visit our web site at
and OE\. FAST-PAGE-MODE operations allow faster data
www.micross.com
operations (READ, WRITE, or READ-MODIFY-WRITE)
within a row address (A0-A9) defined page boundary. The
FAST PAGE MODE
(continued)
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specifications without notice.
1
DRAM
MT4C4001J
GENERAL DESCRIPTION (cont.)
cycle is always initiated with a row address strobe-in by RAS\
followed by a column address strobed-in by CAS\. CAS\ may
be toggled-in by holding RAS\ LOW and strobing-in differ-
ent column addresses, thus executing faster memory cycles.
Returning RAS\ HIGH terminates the FAST PAGE MODE
operation.
Returning RAS\ and CAS\ HIGH terminates a memory cycle
and decreases chip current to a reduced standby level. Also,
the chip is preconditioned for the next cycle during the RAS\
HIGH time. Memory cell data is retained in its corrected stated
by maintaining power and executing any RAS\ cycle (READ,
WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or HIDDEN
REFRESH) so that all 1,024 combinations of RAS\ addresses
(A0-A9) are executed at least every 16ms, regardless of se-
quence. The CBR REFRESH cycle will invoke the internal
refresh counter for automatic RAS\ addressing.
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE\
CAS\
*EARLY-WRITE
DETECTION CIRCUIT
DATA IN
BUFFER
DATA OUT
BUFFER
4
4
4
DQ1
DQ2
DQ3
DQ4
NO. 2 CLOCK
GENERATOR
OE\
10
10
10
ROW
DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLLER
10
COLUMN
DECODER
1024
4
Vcc
Vss
SENSE AMPLIFIERS
I/O GATING
1024 x 4
REFRESH
COUNTER
MEMORY
ARRAY
ROW ADDRESS
BUFFERS (10)
1024
10
RAS\
NO. 1 CLOCK
GENERATOR
NOTE:
WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE)
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specifications without notice.
2
DRAM
MT4C4001J
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ
EARLY-WRITE
READ-WRITE
FAST-PAGE-MODE
READ
FAST-PAGE-MODE
EARLY-WRITE
FAST-PAGE-MODE
READ-WRITE
RAS\-ONLY REFRESH
HIDDEN REFRESH
RAS\
H
L
L
L
L
L
L
L
L
L
L
L H L
L H L
H L
CAS\
H X
L
L
L
H L
H L
H L
H L
H L
H L
H
L
L
L
WE\
X
H
L
H L
H
H
L
L
H L
H L
X
H
L
H
OE\
X
L
X
L H
L
L
X
X
L H
L H
X
L
X
X
R
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
t
DATA IN/OUT
DQ1-DQ4
High-Z
Data Out
Data In
Data Out/Data In
Data Out
Data Out
Data In
Data In
Data Out/Data In
Data Out/Data In
High-Z
Data Out
Data In
High-Z
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
READ
WRITE
CAS\-BEFORE-RAS\ REFRESH
C
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
COL
COL
X
t
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specifications without notice.
3
DRAM
MT4C4001J
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss.................-1.0V to +7.0V
Storage Temperature.......................................-65
o
C to +150
o
C
Power Dissipation.................................................................1W
Short Circuit Output Current...........................................50mA
Lead Temperature (soldering 5 seconds).....................+270
o
C
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operation
section of this specification is not implied.
Exposure to
absolute maximum rating conditions for extended periods may
affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(NOTES: 1, 3, 4, 6, 7) (-55°C < T
A
< 125°C; V
CC
= 5V ±10%)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, All Inputs
Input Low (Logic 0) Voltage, All Inputs
INPUT LEAKAGE CURRENT
Any Input 0V < V
IN
< 5.5V Vcc = 5.5V
(All other pints not under test = 0V)
OUTPUT LEAKAGE CURRENT
(Q is Disabled, 0V < V
OUT
< 5.5V) Vcc = 5.5V
OUTPUT LEVELS
Output High Voltage (I
OUT
= -5mA)
Output Low Voltage (I
OUT
= 4.2mA)
SYM
V
CC
V
IH
V
IL
I
I
I
OZ
V
OH
V
OL
MIN
4.5
2.4
-0.5
-5
-5
2.4
0.4
MAX
5.5
V
CC
+0.5
0.8
5
5
UNITS
V
V
V
μA
μA
V
V
NOTES
PARAMETER/CONDITION
STANDBY CURRENT (TTL)
(RAS\ = CAS\ = V
IH
)
STANDBY CURRENT (CMOS)
(RAS\ = CAS\ = V
CC
-0.2V; all other inputs = V
CC
-0.2V)
OPERATING CURRENT: Random READ/WRITE
Average Power-Supply Current
(RAS\, CAS\, Address Cycling: t
RC
= t
RC
(MIN))
OPERATING CURRENT: FAST PAGE MODE
Average Power-Supply Current
(RAS\ = V
IL
, CAS\, Address Cycling: t
PC
= t
PC
(MIN))
REFRESH CURRENT: RAS\-ONLY
Average Power-Supply Current
(RAS\ Cycling, CAS\ = V
IH
: t
RC
= t
RC
(MIN))
REFRESH CURRENT: CAS\-BEFORE-RAS\
Average Power-Supply Current
(RAS\, CAS\, Address Cycling: t
RC
= t
RC
(MIN))
SYM
I
CC1
I
CC2
I
CC3
-7
4
2
85
MAX
-8
-10
4
2
75
4
2
65
-12
4
2
70
UNITS NOTES
mA
mA
mA
3, 4
I
CC4
60
50
45
40
mA
3, 4
I
CC5
85
75
65
70
mA
3
I
CC6
85
75
65
70
mA
3, 5
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specifications without notice.
4
DRAM
MT4C4001J
CAPACITANCE
PARAMETER
Input Capacitance: A0-A10
Input Capacitance: RAS\, CAS\, WE\, OE\
Input/Output Capacitance: DQ
SYM
C
I1
C
I2
C
IO
MIN
MAX
7
7
8
UNITS
pF
pF
pF
NOTES
2
2
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < T
C
< 125°C; V
CC
= 5V ±10%)
-7
PARAMETER
Random READ or WRITE cycle time
READ-WRITE cycle time
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS\
Access time from CAS\
Access time from column address
Access time from CAS\ precharge
RAS\ pulse width
RAS\ pulse width (FAST PAGE MODE)
RAS\ hold time
RAS\ precharge time
CAS\ pulse width
CAS\ hold time
CAS\ precharge time
CAS\ precharge time (FAST PAGE MODE)
RAS\ to CAS\ delay time
CAS\ to RAS\ precharge time
Row address setup time
Row address hold time
RAS\ to column address delay time
Column address setup time
Column address hold time
Column address hold time (referenced to RAS\)
Column address to RAS\ lead time
Read command setup time
Read command hold time (referenced to CAS\)
Read command hold time (referenced to RAS\)
CAS\ to output in Low-Z
Output buffer turn-off delay
WE\ command setup time
SYM
t
RC
t
RWC
t
PC
t
PRWC
t
RAC
t
CAC
t
AA
t
CPA
t
RAS
t
RASP
t
RSH
t
RP
t
CAS
t
CSH
t
CPN
t
CP
t
RCD
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
AR
t
RAL
t
RCS
t
RCH
t
RRH
t
CLZ
t
OFF
t
WCS
70
70
20
50
20
70
10
10
20
5
0
10
15
0
15
50
35
0
0
0
0
0
0
20
35
50
10,000
MIN
130
180
40
90
70
20
35
35
10,000
100,000
80
80
20
60
20
80
10
10
20
5
0
10
15
0
15
60
40
0
0
0
0
0
0
20
40
60
10,000
MAX
MIN
150
200
45
90
80
20
40
40
10,000
100,000
100
100
25
70
25
100
12
12
25
5
0
15
20
0
20
70
50
0
0
0
0
0
0
20
50
75
10,000
-8
MAX
MIN
190
240
55
110
90
25
45
45
10,000
100,000
120
120
30
90
30
120
15
15
25
10
0
15
20
0
25
85
60
0
0
0
0
0
0
20
60
90
-10
MAX
MIN
220
255
70
140
120
30
60
60
100,000
100,000
-12
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
21, 27
19
19
18
17
16
14
15
NOTES
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specifications without notice.
5
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