H8S/2633 Series
H8S/2633
HD6432633
H8S/2632
HD6432632
H8S/2631
HD6432631
H8S/2633 F-ZTAT™
HD64F2633
Hardware Manual
ADE-602-165B
Rev. 3.0
3/20/01
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
The H8S/2633 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™*
1
), PROM (ZTAT™*
2
), and mask ROM versions
are available, providing a quick and flexible response to conditions from ramp-up through full-
scale volume production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timer, 14-bit PWM timer (PWM), watchdog timer (WDT), serial
communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also
possible to incorporate an on-chip PC bus interface (IIC) as an option.
In addition, DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling
high-speed data transfer without CPU intervention.
Use of the H8S/2633 Series enables easy implementation of compact, high-performance systems
capable of processing large volumes of data.
This manual describes the hardware of the H8S/2633 Series. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.
Main Revisions and Additions in this Edition
Page
7
13
75
Item
1.3.1
1.3.2
3.4
Pin Arrangement
Pin Functions in Each Operating Mode
Pin Functions in Each Operating Mode
Revisions
(See Manual for Details)
Note on FWE pin added
Note 2 added
Table 3-3 Pin Functions in Each
Mode
Port G added
570
15.2.2 Timer Control/Status Register (TCSR)
WDT0 input clock selection
Overflow cycle value amended
571
18.2.4 I
2
C Bus Mode Register (ICMR)
WDT1 input clock selection
Overflow cycle value amended
703
Bits 5 to 3—Transfer clock select
Note added
731
18.3.9 Sample Flowcharts
Figure 18-14 Flowchart for Master
Transmit Mode (Example)
Completely revised
732
Figure 18-15 Flowchart for Master
Receive Mode (Example)
Completely revised
22.1
22.2
22.3
22.4
811
Overview
Register Descriptions
Operation
Flash Memory Overview
Added
Added
Added
Added
Description added
Maximum number of writes
WDT overflow cycle
811
814
815
839
22.7.3 Erase Mode
22.13 Flash Memory Programming and Erasing
Precautions
22.7.2 Program-Verify Mode
Maximum number of writes
amended
Figure 22-12 Program/Program-
Verify Flowchart amended
WDT overflow cycle amended
“Do not perform overwriting. Erase
the memory before reprogramming”
amended
22.7.1 Program Mode
嵌入式系统
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