FemtoClock
®
Crystal-to-LVDS
Frequency Synthesizer
ICS844003I-02
DATA SHEET
General Description
The ICS844003I-02 is a three differential output LVDS Synthesizer
designed to generate Ethernet and PCI Express™ reference clock
frequencies. Using a 31.25MHz, 26.041666MHz, or 25MHz, parallel
resonant crystal, the following frequencies can be generated based
on the settings of four frequency select pins (DIV_SELA[1:0],
DIV_SELB[1:0]): 625MHz, 500MHz, 312.5MHz, 250MHz,
156.25MHz, 125MHz, and 100MHz. The 844003I-02 has two output
banks, Bank A with one differential LVDS output pair and Bank B with
two differential LVDS output pairs.
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above. The
ICS844003I-02 uses IDT’s 3
RD
generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Ethernet jitter requirements. The ICS844003I-02 is
packaged in a 32-pin VFQFN package.
Features
•
•
•
•
•
•
•
•
Three LVDS outputs on two banks, Bank A with one LVDS pair
and Bank B with two LVDS output pairs
Using a 31.25MHz, 26.041666, or 25MHz crystal, the two output
banks can be independently set for 625MHz, 500MHz 312.5MHz,
250MHz, 156.25MHz, 125MHz or 100MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 490MHz to 680MHz
RMS phase jitter at 125MHz (1.875MHz – 20MHz):
0.50ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
REF_CLK
Pin Assignment
32 31 30 29 28 27 26 25
GND
XTAL_IN
XTAL_OUT
XTAL_SEL
VCO_SEL
MR
GND
nc
1
2
3
4
5
6
7
8
9
DIV_SELA1
V
DDO_A
V
DDA
V
DD
V
DD
nc
nc
nc
24
QA0
nQA0
GND
QB0
nQB0
QB1
nQB1
V
DDO_B
ICS844003I-02
32 Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
10 11 12 13 14 15 16
FB_DIV
OEB
DIV_SELA0
DIV_SELB1
DIV_SELB0
GND
OEA
23
22
21
20
19
18
17
Block Diagram
OEA
DIV_SELA[1:0]
VCO_SEL
Pullup
Pulldown, Pullup
Pullup
QA0
Pulldown
REF_CLK
0
0
XTAL_IN
00
01
10
11
÷1
÷2
(default)
÷4
÷5
nQA0
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
490-680MHz
1
QB0
FB_DIV
0 = ÷20 (default)
1 = ÷24
00
01
10
11
÷1
÷2
(default)
÷4
÷5
nQB0
QB1
nQB1
FB_DIV
DIV_SELB[1:0]
MR
OEB
Pulldown
Pulldown, Pullup
Pulldown
Pullup
ICS844003AKI-02 REVISION A FEBRUARY 24, 2011
1
©2011 Integrated Device Technology, Inc.
ICS844003I-02 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 7, 13, 22
2,
3
4
5
6
8, 26, 29, 30
9
10
11
12
14
Name
GND
XTAL_IN
XTAL_OUT
XTAL_SEL
VCO_SEL
MR
nc
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
FB_DIV
Power
Input
Type
Description
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Pullup
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Crystal select pin. Selects between the single-ended REF_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
VCO select pin. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. LVCMOS/LVTTL interface levels.
No connect.
Division select pin for Bank A. LVCMOS/LVTTL interface levels.
Division select pin for Bank A. LVCMOS/LVTTL interface levels.
Division select pin for Bank B. LVCMOS/LVTTL interface levels.
Division select pin for Bank B. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set for ÷20.
When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface
levels.
Output enable Bank B. Active High output enable.
LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable.
LVCMOS/LVTTL interface levels.
Output power supply pin for Bank B outputs.
Differential Bank B output pair. LVDS interface levels.
Differential Bank B output pair. LVDS interface levels.
Differential Bank A output pair. LVDS interface levels.
Output supply pin for Bank A outputs.
Core supply pins.
Analog supply pin.
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to
low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Input
Input
Input
Unused
Input
Input
Input
Input
Input
15
16
17
18, 19
20, 21
23, 24
25
27, 31
28
32
OEB
OEA
V
DDO_B
nQB1, QB1
nQB0, QB0
nQA0, QA0
V
DDO_A
V
DD
V
DDA
REF_CLK
Input
Input
Power
Output
Output
Output
Power
Power
Power
Input
Pullup
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS844003AKI-02 REVISION A FEBRUARY 24, 2011
2
©2011 Integrated Device Technology, Inc.
ICS844003I-02 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Bank A/B Frequency Table
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
25
25
25
25
NOTE: X denotes A or B.
DIV_SELX1
0
0
1
1
0
0
1
1
0
0
1
1
DIV_SELX0
0
1
0
1
0
1
0
1
0
1
0
1
FB_DIV
0
0
0
0
1
1
1
1
0
0
0
0
Feedback
Divider
20
20
20
20
24
24
24
24
20
20
20
20
Output Divider
1
2
4
5
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
4.8
20
10
5
4
Output Frequency
(MHz)
625
312.5
156.25
125
625
312.5
156.25
125
500
250
125
100
Table 3B. Output Bank Configuration Select Function Table
Inputs
DIV_SELX1
0
0
1
1
NOTE: X denotes A or B.
DIV_SELX0
0
1
0
1
Outputs
QA0, nQA0; QB[0:1], nQB[0:1]
÷1
÷2 (default)
÷4
÷5
Table 3C. Feedback Divider Configuration Select Function Table
Input
FB_DIV
0 (default)
1
Feedback Divide
÷20
÷24
Table 3D. VCO_SEL Function Table
Input
VCO_SEL
0
1 (default)
Outputs
PLL is bypassed and the selected reference clock is passed directly to the output dividers.
PLL operation. The selected reference clock is multiplied by the PLL.
3
©2011 Integrated Device Technology, Inc.
ICS844003AKI-02 REVISION A FEBRUARY 24, 2011
ICS844003I-02 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 3E. Master Reset Function Table
Input
MR
0 (default)
1
Outputs
The internal dividers and the outputs are enabled.
The internal dividers are reset. The true outputs (QA0, QBx) are in logic low state, and the inverted outputs (nQA0,
nQBx) are in logic high state (except for ÷1 state, when the device is configured as a buffer).
Table 3F. OEA Select Function Table
Input
OEA
0
1 (default)
Outputs
QA0, nQA0
High-Impedance
Active
NOTE: OEA is an asynchronous control.
Table 3G. OEB Select Function Table
Input
OEB
0
1 (default)
Outputs
QB[0:1], nQB[0:1]
High-Impedance
Active
NOTE: OEB is an asynchronous control.
Table 3H. XTAL_SEL Function Table
Input
XTAL_SEL
0
1 (default)
QB[0:1], nQB[0:1]
The REF_CLK input is selected as the reference clock.
The crystal Interface is selected as the reference clock.
Operation
ICS844003AKI-02 REVISION A FEBRUARY 24, 2011
4
©2011 Integrated Device Technology, Inc.
ICS844003I-02 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
3.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
10mA
15mA
33.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO_A
= V
DDO_B
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO_A,
V
DDO_B
I
DD
I
DDA
I
DDO_A
+ I
DDO_B
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.97
V
DD
– 0.20
2.97
Typical
3.3
3.3
3.3
Maximum
3.63
V
DD
3.63
140
20
70
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO_A
= V
DDO_B
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
REF_CLK, MR, FB_DIV,
DIV_SELA1, DIV_SELB1
I
IH
Input
High Current
OEA, OEB,
VCO_SEL, XTAL_SEL,
DIV_SELA0, DIV_SELB0
REF_CLK, MR, FB_DIV,
DIV_SELA1, DIV_SELB1
I
IL
Input
Low Current
OEA, OEB,
VCO_SEL, XTAL_SEL,
DIV_SELA0, DIV_SELB0
V
DD
= V
IN
= 3.63V
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
V
DD
= V
IN
= 3.63V
5
µA
V
DD
= 3.465V, V
IN
= 0V
-5
µA
V
DD
= 3.465V, V
IN
= 0V
-150
µA
ICS844003AKI-02 REVISION A FEBRUARY 24, 2011
5
©2011 Integrated Device Technology, Inc.
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