Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
Data Sheet
840S05I
General Description
The 840S05I is a five output LVCMOS/LVTTL Frequency
Synthesizer accepting crystal or single-ended reference clock
inputs. The 840S05I uses a 25MHz parallel resonant crystal to
generate 33.33MHz – 166.67MHz clock signals, replacing solutions
requiring multiple oscillator and fan-out buffer solution. The device
supports output slew rate control with two slew select pins
(SLEW[1:0]). The VCO operates at a frequency of 2GHz. The device
has 2 output banks, Bank A with two 33.33MHz – 166.67MHz
LVCMOS/LVTTL outputs and Bank B with two 33.33MHz –
166.67MHz LVCMOS/LVTTL outputs.
The two banks have their own dedicated frequency select pins and
can be independently set for frequencies in the ranges mentioned
above. Designed for networking and industrial applications, the
840S05I can also drive the high-speed clock inputs of
communication processors, DSPs, switches and bridges.
Features
•
•
•
•
•
•
•
•
•
Four single-ended LVCMOS/LVTTL clock outputs
One REF_OUT LVCMOS/LVTTL clock output
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference input
Supports the following output frequencies on either bank:
33.33MHz, 50MHz, 66.67MHz, 83.33MHz, 100MHz, 125MHz,
133.33MHz, and 166.67MHz
VCO: 2GHz
Slew rate control
Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
F_SELA[0,
2]
Pullup
F_SELA1
Pulldown
25MHz
2
Pin Assignment
V
DDO_A
GND
QA0
QA1
QB0
V
DDO_B
GND
QB1
QA0
÷NA
0
QA1
XTAL_IN
V
DD
nc
GND
QB0
24 23 22 21 20 19 18 17
25
16
26
27
28
29
30
31
32
1
V
DDA
2
V
DD
3
XTAL_OUT
4
XTAL_IN
5
GND
6
REF_SEL
7
REF_IN
8
F_SELB2
15
14
13
12
11
10
9
F_SELB0
MR/nOE
F_SELB1
GND
nc
REF_OUT
V
DDO_REF
nREF_OE
OSC
XTAL_OUT
PLL
VCO
2GHz
1
÷NB
QB1
F_SELA0
F_SELA1
SLEW0
SLEW1
F_SELA2
REF_IN
Pulldown
REF_SEL
Pulldown
2
M =
÷
80
SLEW[1:0]
Pulldown
MR/nOE
Pulldown
F_SELB[2:0]
Pulldown
nREF_OE
Pullup
3
REF_OUT
840S05I
32-Lead TQFP, E-Pad
7mm x 7mm x 1mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A April 11, 2016
840S05I Data Sheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2, 25
3,
4
5, 13,
20, 24, 27
6
7
8,
14,
16
9
10
11
12, 26
15
17
18, 19
21
22, 23
28,
32
29
30,
31
Name
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
GND
REF_SEL
REF_IN
F_SELB2,
F_SELB1,
F_SELB0
nREF_OE
V
DDO_REF
REF_OUT
nc
MR/nOE
V
DDO_B
QB1, QB0
V
DDO_A
QA1, QA0
F_SELA0,
F_SELA2
F_SELA1
SLEW0,
SLEW1
Power
Power
Input
Power
Input
Input
Input
Pulldown
Pulldown
Pulldown
Type
Description
Analog supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Power supply ground.
Reference select pin. See Table 3C. LVCMOS/LVTTL interface levels.
Single-ended 25MHz reference clock input. LVCMOS/LVTTL interface levels.
Frequency select pins for Bank B outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
Active low REF_OUT enable/disable pin. See Table 3D.
LVCMOS/LVTTL interface levels.
Output supply pin for REF_OUT clock output.
Single-ended LVCMOS/LVTTL reference clock output.
No connect.
Pulldown
Active HIGH Master Reset. Active LOW output enable. See Table 3E.
LVCMOS/LVTTL interface levels.
Output supply pin for QBx outputs.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
Output supply pin for QAx outputs.
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
Pullup
Pulldown
Pulldown
Frequency select pins for Bank A outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
Frequency select pin for Bank A outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
Slew rate select pins for LVCMOS/LVTTL clock output. See Table 3B.
LVCMOS/LVTTL interface levels.
Input
Power
Output
Unused
Input
Power
Output
Power
Output
Input
Input
Input
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc
2
Revision A April 11, 2016
840S05I Data Sheet
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
QA[1:0],
QB[1:0]
QA[1:0],
QB[1:0]
QA[1:0],
QB[1:0]
QA[1:0],
QB[1:0]
QA[1:0],
QB[1:0]
REF_OUT
R
PULLUP
R
PULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
QA[1:0],
QB[1:0]
R
OUT
;
NOTE 1
Output
Impedance
QA[1:0],
QB[1:0]
REF_OUT
REF_OUT
NOTE 1: Characterized with SLEW[1:0] = 00.
V
DDO_A
, V
DDO_B
= 3.3V
V
DDO_A
, V
DDO_B
= 2.5V
V
DDO_REF
= 3.3V
V
DDO_REF
= 2.5V
SLEW[1:0] = 00
V
DD
, V
DDA
, V
DDO_REF
,
V
DDO_A
, V
DDO_B
= 3.465V
SLEW[1:0] = 01
V
DD
, V
DDA
, V
DDO_REF
,
V
DDO_A
, V
DDO_B
= 3.465V
SLEW[1:0] = 10
V
DD
, V
DDA
, V
DDO_REF
,
V
DDO_A
, V
DDO_B
= 3.465V
SLEW[1:0] = 11
V
DD
, V
DDA
, V
DDO_REF
,
V
DDO_A
, V
DDO_B
= 3.465V
V
DD
, V
DDA
= 3.465V
V
DDO_REF
, V
DDO_A
, V
DDO_B
= 2.625V
V
DD
, V
DDA
= 3.465V
V
DDO_REF
, V
DDO_A
, V
DDO_B
= 3.465V or 2.625V
Test Conditions
Minimum
Typical
2
6.5
Maximum
Units
pF
pF
10.5
pF
C
PD
Power
Dissipation
Capacitance
13
pF
16
pF
5
pF
4
51
51
18
21
22
25
pF
k
k
Function Tables
Table 3A. Frequency Select Function Table
Inputs
F_SELA2,
F_SELB2
L
L
L
L
H
H
H
H
F_SELA1,
F_SELB1
L
L
H
H
L
L
H
H
F_SELA0,
F_SELB0
L
H
L
H
L
H
L
H
M Divider
Value
80
80
80
80
80
80
80
80
NA, NB
Divider Value
60
40
30
24
20
16
15
12
Output Frequency
QA[1:0] (MHz)
33.33
50
66.67
83.33
100
125 (default)
133.33
166.67
QB[1:0] (MHz)
33.33 (default)
50
66.67
83.33
100
125
133.33
166.67
NOTE: Using 25MHz reference.
©2016 Integrated Device Technology, Inc
3
Revision A April 11, 2016
840S05I Data Sheet
Table 3B. Slew Rate Function Table
Setting
SLEW1
0
0
1
1
SLEW0
0
1
0
1
Slew Rate
(v/ns)
3.5 (Default)
2.6
1.8
1.0
NOTE: Typical values for V
DDO_A
, V
DDO_B
= 3.3V. Refer to the AC Characteristics Table for more details.
Table 3C. REF_SEL Function Table
REF_SEL
0 (Default)
1
Input Reference
XTAL_IN
REF_IN
Table 3D. nREF_OE Function Table
nREF_OE
0
1 (Default)
REF_OUT State
REF_OUT enabled
REF_OUT disabled (Logic LOW)
Table 3E. MR/nOE Function Table
MR/nOE
0 (Default)
1
Function
QA and QB outputs enabled.
Device reset, QA and QB outputs disabled (Logic LOW).
NOTE: A MR/OE pulse is required after device power-up to guarantee functionality.
©2016 Integrated Device Technology, Inc
4
Revision A April 11, 2016
840S05I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
36.2C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO_REF
= V
DDO_A
= V
DDO_B
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO_A,
V
DDO_B,
V
DDO_REF
I
DD
I
DDA
I
DDO_A
,
I
DDO_B
I
DDO_REF
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Output Supply Current
SLEW[1:0] = 11, QA[1:0], QB[1:0] = 166.67MHz;
REF_OUT = 25MHz, Outputs Not Loaded
Outputs Not Loaded
Test Conditions
Minimum
3.135
V
DD
– 0.20
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
160
20
30
2
Units
V
V
V
mA
mA
mA
mA
NOTE: All parameters specified for inputs and outputs under static conditions, unless otherwise noted.
Table 4B. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO_REF
= V
DDO_A
= V
DDO_B
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO_A,
V
DDO_B,
V
DDO_REF
I
DD
I
DDA
I
DDO_A
,
I
DDO_B
I
DDO_REF
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Output Supply Current
SLEW[1:0] = 11, QA[1:0], QB[1:0] = 166.67MHz;
REF_OUT = 25MHz, Outputs Not Loaded
Outputs Not Loaded
Test Conditions
Minimum
3.135
V
DD
– 0.20
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
2.625
160
20
10
1
Units
V
V
V
mA
mA
mA
mA
NOTE: All parameters specified for inputs and outputs under static conditions, unless otherwise noted.
©2016 Integrated Device Technology, Inc
5
Revision A April 11, 2016
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