GS82032AT/Q-200/180/166/133/100
TQFP, QFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP or QFP package
-200
-180
-166
-133
Pipeline tCycle 5 ns
5.5 ns
6 ns
7.5 ns
3-1-1-1 t
KQ
3 ns
3.2 ns 3.5 ns
4 ns
I
DD
170 mA 155 mA 140 mA 115 mA
Flow tCycle 8.8 ns 9.1 ns
10 ns
12 ns
Through t
KQ
7.5 ns
8 ns
8.5 ns
10 ns
2-1-1-1 I
DD
100 mA 100 mA 90 mA 80 mA
-100
10 ns
5 ns
90 mA
15 ns
12 ns
65 mA
64K x 32
2M Synchronous Burst SRAM
Flow Through/Pipeline Reads
200 MHz–100 MHz
7.5 ns–12 ns
3.3 V V
DD
3.3 V and 2.5 V I/O
The function of the Data Output Register can be controlled by
the user via the FT mode pin (Pin 14 in the TQFP). Holding
the FT mode pin low places the RAM in Flow Through mode,
causing output data to bypass the Data Output Register.
Holding FT high places the RAM in Pipelined mode,
activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS82032A is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Functional Description
Applications
The GS82032A is a 2,097,152-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS82032A operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Rev: 1.08 2/2001
1/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-200/180/166/133/100
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
87
93, 94
95, 96
89
88
98, 92
97
86
83
84, 85
64
14
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
Symbol
A
0
, A
1
A
2
–A
15
DQ
A1
–DQ
A8
DQ
B1
–DQ
B8
DQ
C1
–DQ
C8
DQ
D1
–DQ
D8
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
Type
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
I/O
Data Input and Output pins
No Connect
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.08 2/2001
3/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-200/180/166/133/100
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Pin Name
LBO
FT
ZZ
State
L
H or NC
L
H or NC
L or NC
H
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Note:
There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
1st address
2nd address
3rd address
4th address
I
nterleaved Burst Sequence
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock
.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
Read
Read
Write byte
A
Write byte
B
Write byte
C
Write byte
D
Write all bytes
Write all bytes
GW
H
H
H
H
H
H
H
L
BW
H
L
L
L
L
L
L
X
B
A
X
H
L
H
H
H
L
X
B
B
X
H
H
L
H
H
L
X
B
C
X
H
H
H
L
H
L
X
B
D
X
H
H
H
H
L
L
X
Notes
1
1
2, 3
2, 3
2, 3, 4
2, 3, 4
2, 3, 4
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.08 2/2001
5/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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