Standard Products
UT04VS33P Voltage Supervisor
Preliminary Data Sheet
February 27, 2013
www.aeroflex.com/VoltSupv
FEATURES
3.0V to 3.6V Operating voltage range
6 Fixed Threshold Voltage Monitors (3.3V, 2.5V, 1.8V, 1.5V,
1.2V, 1.0V)
Fixed & Adjustable Threshold Voltage Select modes
Threshold Voltage Select with TH0, TH1 pins
Adjustable RESET Timeout with external capacitor
Independent Voltage Monitoring and Sequencing
Manual Reset Input Pin
Active Low and Active High RESET pins
Output Voltages Open Drain
Two VOUTS active high and two VOUTS programmable
with INV Pin
RESET, RESETB Outputs Open Drain
Over-voltage Detection Mode
Operating Temperature Range -55
o
C to +125
o
C
Low Power Typical 1000μA
Tolerance Select Input Pin (5% & 10%)
RESET, RESETB, VOUT1, VOUT2, VOUT3 and VOUT4
guaranteed to be in the correct state for V
DD
down to 1.2V
INTRODUCTION
The UT04VS33P is a radiation-hardened Voltage Supervisor
which simultaneously monitors up to four supply levels utilized
in a system, providing status output for each signal, VOUTx, as
well as, a system reset signal if any of the monitored signals
moves out of range. To set the monitor trip points, the TH0 and
TH1 pins allow the selection of three sets of preset threshold
levels per channel, determined by an internal bandgap voltage
reference, to reduce supply and temperature variance, and a
fourth selection which allows the user to determine the level for
each channel. There are two modes of operation, determined by
the OVSH pin. In the first mode, when the OVSH pin is
connected to VSS, four independent supplies are monitored for
an under-voltage condition. In the second mode when the OVSH
pin is connected to VDD, then under-voltage and over-voltage
of the inputs are monitored. In this mode, two supplies can be
monitored using channels 1 and 3 or channels 2 and 4,
respectively. For flexibility, both system RESET and RESETB
outputs are available for interfacing to the system. Each channel
has an enable, ENx, allowing use of one, two, three or all four
monitor channels.
The margin (or tolerance) to the given threshold voltage, for
under-voltage monitoring, is determined by the setting of the
TOL pin. The logic sense of the channel 3 and 4 outputs can be
inverted by setting the INV pin, appropriately. Also, MRB,
master reset, provides a means for a manual input to activate the
RESET signals. In addition, the user can adjust two timing
parameters by the addition of external capacitors to the device.
These are the response times of the channel VOUTx signal when
the associated input returns to a valid level, implemented by a
capacitor connected to CDLYx and the time to clear RESET (and
RESETB) when a channel enable or input level becomes valid;
implemented by CRESET.
APPLICATION
The UT04VS33P supervisory circuit reduces the complexity and
number of circuits required to monitor power supply and battery
functions in microprocessor, DSP, microcontroller, ASIC and
FPGA systems. The UT04VS33P supervisory circuit
significantly improves system reliability and accuracy over
comparable systems that use separate ICs or discrete
components.
Packaging options:
- 28-lead ceramic dual flatpack
Operational environment:
- Total dose: 300 krad(Si)
- SEL Immune: <110 MeV-cm
2
/mg @125
o
C
Exceptional SET Immunity (reference: Aeroflex Single
Event Transient Characterization Report for the
UT04VS33P and UT04VS50P Voltage Supervisor
Products)
Standard Microelectronics Drawing (SMD) 5962-13206
- QML Q and V
1
CDLY1
CDLY2
CDLY3
CDLY4
INV
VDD
VTH MONITOR
VIN1
+
-
Drivers
DELAY
VOUT1
VIN2
+
-
DELAY
VOUT2
VIN3
+
-
DELAY
VOUT3
VIN4
OVSH
EN1
EN2
EN3
EN4
+
-
DELAY
VOUT4
RESETB
RESET
THRESHOLD
SELECT
VREF
RESET
DELAY
TH0
TH1
TOL
VSS
CRESET
MRB
Figure 1. UT04VS33P Block Diagram
EN1
VIN1
EN3
VIN3
NC
OVSH
TH1
TH0
TOL
EN2
VIN2
EN4
VIN4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
UT04VS33P
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VOUT1
CDLY1
VOUT3
CDLY3
MRB
INV
RESETB
CRESET
RESET
VOUT2
CDLY2
VOUT4
CDLY4
Figure 2. UT04VS33P Pin Configuration
2
PIN DESCRIPTIONS
Number
1
Pins
EN1
Type
Digital Input
Description
Active high enable for VIN1. Setting this pin low forces VOUT1 low
regardless of the value of VIN1. Setting this pin high enables the
monitor circuitry for VIN1.
Analog input VIN1. When enabled the voltage input is monitored for
an under-voltage condition; see Functional Descriptions - Thresholds,
Over-voltage Setting/Tolerance. The condition is output on VOUT1.
Active high enable for VIN3. Setting this pin low forces VOUT3 low
when OVSH=0 (VOUT3 is forced low when OVSH=1) regardless of
the value of VIN3. Setting this pin high enables the monitor circuitry
for VIN3.
Analog input VIN3. When enabled and dependent on the mode of
operation (OVSH), the voltage input is monitored for an under-voltage
or over-voltage condition; see Functional Descriptions - Thresholds,
Over-voltage Setting/Tolerance. The condition is output on VOUT3
when OVSH=0 and on VOUT1 when OVSH=1.
2
VIN1
Analog Input
3
EN3
Digital Input
4
VIN3
Analog Input
5
6
NC
OVSH
NC
Digital Input
Over-voltage pin. When OVSH = 1, the over-voltage mode is enabled.
This allows for the monitoring of both over-voltage and under-voltage
of two supplies. Inputs VIN1 and VIN2 function normally, while VIN3
is used to monitor an over-voltage condition in conjunction with the
VIN1 source and VIN4 likewise for the VIN2 source. See Functional
Descriptions - Thresholds, Over-voltage Setting/Tolerance. When
OVSH=0 all four inputs, VIN1, VIN2, VIN3 and VIN4 monitor under-
voltage.
Digital Threshold select1. Used with TH0 to select one of four analog
input voltage thresholds. (See Table 2)
Digital Threshold select0. Used with TH1 to select one of four analog
input voltage thresholds. (See Table 2)
Threshold tolerance select sets the accuracy of the threshold to 5%
below the nominal value by connecting TOL to logic 0. Connecting
TOL to logic 1 sets the threshold voltage to 10% below the nominal
value.
Active high enable for VIN2. Setting this pin low forces VOUT2 low
regardless of the value of VIN2. Setting this pin high enables the
monitor circuitry for VIN2.
Analog input VIN2. When enabled, the voltage input is monitored for
an under-voltage condition; see Functional Descriptions - Thresholds,
Over-voltage Setting/Tolerance.The condition is output on VOUT2.
7
TH1
Digital Input
8
TH0
Digital Input
9
TOL
Digital Input
10
EN2
Digital Input
11
VIN2
Analog Input
3
Number
12
Pins
EN4
Type
Digital Input
Description
Active high enable for VIN4. Setting this pin low forces VOUT4 low
when OVSH=0 (VOUT4 is forced low when OVSH=1) regardless of
the value of VIN4. Setting this pin high enables the monitor circuitry
for VIN4.
Analog input VIN4. When enabled and dependent on the mode of
operation (OVSH), the voltage input is monitored for an under-voltage
or over-voltage condition; see Functional Descriptions - Thresholds,
Over-voltage Setting/Tolerance. The condition is output on VOUT4
when OVSH=0 and on VOUT2 when OVSH=1.
Ground. This pin must be tied to system ground to establish a reference
for voltage detection.
External capacitor delay connection. Allows adjustment of the
VOUT4 timing after VIN4 becomes valid, when OVSH = 0. See
Functional Descriptions - CDLY timing section.
Output of VIN4 monitor when OVSH = 0; inactive when OVSH=1.
With INV=0, logic 1 indicates that the VIN4 input is at a valid level.
With INV=1, logic 0 indicates that VIN4 is at a valid level. Device
contains active pull-down device; requires external pull-up.
External capacitor delay connection. Allows adjustment of the
VOUT2 timing after VIN2 becomes valid. See Functional
Descriptions - CDLY timing section.
When OVSH=0, it indicates the signal state of the VIN2 monitor.
When OVSH=1, it indicates the combined signal states for VIN2 and
VIN4 (under-voltage and over-voltage detection). See Functional
Descriptions - Thresholds, Device contains active pull-down device;
requires external pull-up.
Active high output indicating a system reset condition is activated by
appropriate condition on VOUTx, ENx, or MRB pin. See discussion
for state changes and timing information. Device contains active pull-
down device; requires external pull-up.
External capacitor delay connection. Allows adjustment of RESET
timeout, which is the time RESET is held after all reset input conditions
are cleared. See Functional Description - CRESET timing section.
Active low output indicating a system reset condition is activated by
appropriate condition on VOUTx, ENx, or MRB pin. See discussion
for state changes and timing information. Device contains active pull-
down device; requires external pull-up.
When logic 1, inverts the sense of the VOUT3 and VOUT4 outputs.
Master Reset active low input. This forces the RESET/RESETB pins
to their active state. See discussion for timing information.
13
VIN4
Analog Input
14
VSS
Supply GND
15
CDLY4
Analog Output
16
VOUT4
Open Drain
Digital Output
17
CDLY2
Analog Output
18
VOUT2
Open Drain
Digital Output
19
RESET
Open Drain
Digital Output
20
CRESET
Analog Output
21
RESETB
Open Drain
Digital Output
22
23
INV
MRB
Digital Input
Digital Input
Internal Pull-up
4
Number
24
Pins
CDLY3
Type
Analog Output
Description
External capacitor delay connection. Allows adjustment of the
VOUT3 timing after VIN3 becomes valid when OVSH=0. See
Functional Descriptions - CDLY timing section.
Output of VIN3 monitor when OVSH=0; inactive when OVSH=1.
With INV=0, logic 1 indicates that the VIN3 input is at a valid level.
With INV=1, logic 0 indicates that VIN3 is at a valid level. Device
contains active pull-down device; requires external pull-up.
External capacitor delay connection. Allows adjustment of the
VOUT1 timing after VIN1 becomes valid. See Functional
Descriptions - CDLY timing section.
When OVSH=0, it indicates the signal state of the VIN1 monitor.
When OVSH=1, it indicates the combined signal states for VIN1 and
VIN3 (under-voltage and over-voltage detection). See Functional
Descriptions - Thresholds, Device contains active pull-down device;
requires external pull-up.
Supply voltage, 3.0 to 3.6V.
25
VOUT3
Open Drain
Digital Output
26
CDLY1
Analog Output
27
VOUT1
Open Drain
Digital Output
28
VDD
Supply
5
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