DATA SHEET
Integrated
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V
Circuit
LVPECL/ECL
Systems, Inc.
BUFFER
FANOUT
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
F
EATURES
•
2 differential 2.5V/3.3V LVPECL / ECL outputs
•
1 differential PCLK, nPCLK input pair
•
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: >3GHz
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
•
Output skew: 5ps (typical)
•
Part-to-part skew: 130ps (maximum)
•
Propagation delay: 390ps (maximum)
•
Additive phase jitter, RMS: 0.06ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
•
-40°C to 85°C ambient operating temperature
•
Available in both Standard and lead-free RoHS compliant
packages
ICS853011
ICS853011
G
ENERAL
D
ESCRIPTION
The ICS853011 is a low skew, high perfor-
mance 1-to-2 Differential-to-2.5V/3.3V LVPECL/
HiPerClockS™
ECL Fanout Buffer and a member of the
HiPerClockS™ family of High Perfor mance
Clock Solutions from ICS. The ICS853011
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and par t-to-par t skew
characteristics make the ICS853011 ideal for those
clock distribution applications demanding well defined
perfor mance and repeatability.
IC
S
B
LOCK
D
IAGRAM
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
Vcc
PCLK
nPCLK
V
EE
ICS853011
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
ICS853011
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
853011BM
www.icst.com/products/hiperclocks.html
1
REV. C NOVEMBER 2, 2005
IDT™ / ICS™
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
1
ICS853011
ICS853011
Circuit
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
ICS853011
Systems, Inc.
L
OW
S
KEW
, 1-
TO
-2
TSD
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
Type
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Pullup/
Pulldown
Pulldown
Clock input. V
CC
/2 default when left floating. LVPECL interface levels.
Clock input. Default LOW when left floating. LVPECL interface levels.
Positive supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
V
EE
nPCLK
PCLK
V
CC
Output
Output
Power
Input
Input
Power
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VCC/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
kΩ
kΩ
853011BM
www.icst.com/products/hiperclocks.html
2
REV. C NOVEMBER 2, 2005
IDT™ / ICS™
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
2
ICS853011
ICS853011
Circuit
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
ICS853011
Systems, Inc.
L
OW
S
KEW
, 1-
TO
-2
TSD
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V (LVPECL mode, V
EE
= 0)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, V
CC
= 0)
to the device. These ratings are stress specifi-
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
- 0.5V
50mA
100mA
-65°C to 150°C
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Operating Temperature Range, TA -40°C to +85°C
Package Thermal Impedance,
θ
JA
112.7°C/W (0 lfpm)
(Junction-to-Ambient) for 8 Lead SOIC
Package Thermal Impedance,
θ
JA
101.7°C/W (0 m/s)
(Junction-to-Ambient) for 8 Lead TSSOP
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V; V
EE
= 0V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3. 3
Maximum
3.8
25
Units
V
mA
T
ABLE
3B. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
PCLK, nPCLK
High Current
Input
Low Current
PCLK
-40°C
Min
2.175
1.405
150
1.2
25°C
Max
2.38
1.68
1200
3.3
150
85°C
Max
2.37
1.615
1200
3.3
150
Typ
2.275
1.545
800
Mi n
2.225
1.425
150
1. 2
Typ
2.295
1.52
800
Min
2.22
1.44
150
1.2
Typ
2.295
1.535
800
Max
2.365
1.63
1200
3.3
150
Units
V
V
V
V
µA
µA
µA
-10
-10
-10
-150
-150
nPCLK
-150
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
853011BM
www.icst.com/products/hiperclocks.html
3
REV. C NOVEMBER 2, 2005
IDT™ / ICS™
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3
ICS853011
ICS853011
Circuit
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
ICS853011
Systems, Inc.
L
OW
S
KEW
, 1-
TO
-2
TSD
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
-40°C
Typ
1.475
0.745
800
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
PCLK, nPCLK
High Current
PCLK
Input
Low Current nPCLK
Min
1.375
0.605
150
1.2
Max
1.58
0.88
1200
2. 5
150
Min
1.425
0.625
150
1.2
25°C
Typ
1.495
0.72
800
Max
1.57
0.815
1200
2.5
150
Min
1.42
0.64
150
1.2
85°C
Typ
1.495
0.735
80 0
Ma x
1.565
0.83
1200
2.5
150
Units
V
V
V
V
µA
µA
µA
-10
-150
-10
-150
-10
-150
For notes see above Table 3B, 3.3V LVPECL DC Characteristics.
T
ABLE
3D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-2.375V
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
PCLK, nPCLK
High Current
Input
PCLK
-40°C
Min
-1.125
-1.895
150
V
EE
+1.2V
25°C
Max
-0.92
-1.62
1200
0
150
85°C
Max
-0.93
-1.685
1200
0
150
Typ
-1.025
-1.755
800
Min
-1.075
-1.875
150
V
EE
+1.2V
Typ
-1.005
-1.78
800
Min
-1.08
-1.86
150
V
EE
+1.2V
Typ
-1.005
-1.765
800
Max
-0.935
-1.67
1200
0
150
Units
V
V
V
V
µA
µA
µA
-10
-10
-10
-150
-150
-150
Low Current nPCLK
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-2.375V
Symbol
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section,
Integration Range: 12KHz to 20MHz
Output Rise/Fall Time
20% to 80%
70
245
5
Min
OR
V
CC
= 2.375
TO
3.8V; V
EE
= 0V
-40°C
Typ
Max
>3
375
20
130
0.06
25 0
80
26 0
Min
25°C
Typ
Max
>3
390
5
20
130
0.06
250
100
275
Min
85°C
Typ
Max
>3
415
5
20
150
0.06
25 0
Units
GHz
ps
ps
ps
ps
ps
odc
Output Duty Cycle
f
≤
1GHz
48
50
52
48
50
52
48
50
52
%
All parameters are measured at f
≤
1.7GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853011BM
www.icst.com/products/hiperclocks.html
4
REV. C NOVEMBER 2, 2005
IDT™ / ICS™
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
4
ICS853011
ICS853011
Circuit
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
ICS853011
Systems, Inc.
L
OW
S
KEW
, 1-
TO
-2
TSD
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
155.52MHz@12kHz to 20MHz
= 0.06ps (typical)
SSB P
HASE
N
OISE
dBc/H
Z
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853011BM
www.icst.com/products/hiperclocks.html
5
REV. C NOVEMBER 2, 2005
IDT™ / ICS™
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
5
ICS853011
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