IS61SPS25632T/D
IS61SPS25636T/D
IS61SPS51218T
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINE,
SINGLE-CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• Single cycle deselect
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
ISSI
DECEMBER 2003
®
DESCRIPTION
The
ISSI
IS61SPS25632, IS61SPS25636, and IS61SPS51218
are high-speed, low-power synchronous static RAMs de-
signed to provide a burstable, high-performance memory for
communication and networking applications. The
IS61SPS25632 is organized as 262,144 words by 32 bits
and the IS61SPS25636 is organized as 262,144 words by 36
bits. The IS61SPS51218 is organized as 524,288 words by
18 bits. Fabricated with
ISSI
's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-133
4
7.5
133
Units
ns
ns
MHz
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/01/2003
1
IS61SPS25632T/D
IS61SPS25636T/D
IS61SPS51218T
PIN CONFIGURATION
100-Pin TQFP (D Version)
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
A17
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
ISSI
®
NC
DQc1
DQc2
VDDQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VDDQ
DQc7
DQc8
NC
VDD
NC
GND
DQd1
DQd2
VDDQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VDDQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VDDQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VDDQ
DQb2
DQb1
GND
NC
VDD
ZZ
DQa8
DQa7
VDDQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VDDQ
DQa2
DQa1
NC
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
3
GW
CE,
CE2
OE
DQa-DQd
MODE
V
DD
GND
V
DDQ
ZZ
GND
Q
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
Snooze Enable
Isolated Output Buffer Ground
A2-A17
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/01/03
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
256K x 32
IS61SPS25632T/D
IS61SPS25636T/D
IS61SPS51218T
PIN CONFIGURATION
100-Pin TQFP (T Version)
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
ISSI
®
NC
DQc1
DQc2
VDDQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VDDQ
DQc7
DQc8
NC
VDD
NC
GND
DQd1
DQd2
VDDQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VDDQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VDDQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VDDQ
DQb2
DQb1
GND
NC
VDD
ZZ
DQa8
DQa7
VDDQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VDDQ
DQa2
DQa1
NC
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
GW
OE
DQa-DQd
MODE
V
DD
GND
V
DDQ
ZZ
GND
Q
Synchronous Global Write Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
Snooze Enable
Isolated Output Buffer Ground
A2-A17
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
4
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VDD
NC
A17
A10
A11
A12
A13
A14
A15
A16
256K x 32
CE,
CE2,
CE2
Synchronous Chip Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/01/03
IS61SPS25632T/D
IS61SPS25636T/D
IS61SPS51218T
PIN CONFIGURATION
100-Pin TQFP (D Version)
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
A17
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
ISSI
®
DQPc
DQc1
DQc2
VDDQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VDDQ
DQc7
DQc8
NC
VDD
NC
GND
DQd1
DQd2
VDDQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VDDQ
DQd7
DQd8
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
DQPb
DQb8
DQb7
VDDQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VDDQ
DQb2
DQb1
GND
NC
VDD
ZZ
DQa8
DQa7
VDDQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VDDQ
DQa2
DQa1
DQPa
256K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE,
CE2
OE
DQa-DQd
MODE
V
DD
GND
V
DDQ
ZZ
DQPa-DQPd
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
Snooze Enable
Parity Data I/O
A2-A17
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/01/03
5
stm32/stm8
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