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5962H9656602VXC

产品描述Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDFP16, BOTTOM-BRAZED, CERAMIC, DFP-16
产品类别逻辑    逻辑   
文件大小167KB,共11页
制造商Cobham Semiconductor Solutions
下载文档 详细参数 全文预览

5962H9656602VXC概述

Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDFP16, BOTTOM-BRAZED, CERAMIC, DFP-16

5962H9656602VXC规格参数

参数名称属性值
零件包装代码DFP
包装说明DFP,
针数16
Reach Compliance Codeunknown
ECCN代码3A001.A.1.A
计数方向BIDIRECTIONAL
系列AC
JESD-30 代码R-CDFP-F16
JESD-609代码e4
负载/预设输入YES
逻辑集成电路类型BINARY COUNTER
工作模式SYNCHRONOUS
位数4
功能数量1
端子数量16
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DFP
封装形状RECTANGULAR
封装形式FLATPACK
传播延迟(tpd)27 ns
认证状态Not Qualified
筛选级别MIL-PRF-38535 Class V
座面最大高度2.921 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)4.5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层GOLD
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
总剂量1M Rad(Si) V
触发器类型POSITIVE EDGE
宽度6.731 mm
最小 fmax80 MHz
Base Number Matches1

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UT54ACS193E
Synchronous 4-Bit Up-Down Dual Clock Counter
July 2013
www.aeroflex.com/Logic
Datasheet
FEATURES
Look-ahead circuitry enhances cascaded counters
Fully synchronous in count modes
Parallel asynchronous load for modulo-N count lengths
Asynchronous clear
m
CRH CMOS process
- Latchup immune
High speed
Low power consumption
Wide power supply operating range of 3.0V to 5.5V
Available QML Q or V processes
16-lead flatpack
UT54ACS193E - SMD 5962-96566
The device is characterized over full HiRel temperature range
of -55
o
C to +125
o
C.
PINOUT
16-Lead Flatpack
TopView
B
Q
B
Q
A
DOWN
UP
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
A
CLR
BO
CO
LOAD
C
D
DESCRIPTION
The UT54ACS193E is a synchronous 4-bit, reversible up-down
binary counter. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change
coincident with each other when instructed. Synchronous
operation eliminates the output counting spikes normally
associated with asynchronous counters.
The outputs of the four flip-flops are triggered on a low-to-high-
level transition of either count input (Up or Down). The direc-
tion of the counting is determined by which count input is pulsed
while the other count input is high.
The counter is fully programmable. The outputs may be preset
to either level by placing a low on the load input and entering
the desired data at the data inputs. The outputs will change to
agree with the data inputs independently of the count pulses.
Asynchronous loading allows the counter to be used as modulo-
N divider by simply modifying the count length with the preset
inputs.
A clear input has been provided that forces all outputs to the
low level when a high level is applied. The clear function is
independent of the count and the load inputs.
The counter is designed for efficient cascading without the need
for external circuitry. The borrow output (BO) produces a low-
level pulse while the count is zero and the down input is low.
Similarly, the carry output (CO) produces a low-level pulse
while the count is maximum and the up input is low.
1
FUNCTION TABLE
FUNCTION
Count Up
Count Down
Reset
Load Preset
Input
CLOCK
UP
H
X
X
CLOCK
DOWN
H
X
X
CLR
L
L
H
L
LOAD
H
H
X
L

 
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