Tripath Technology, Inc. - Technical Information
TA2021B
STEREO 25W (4Ω) CLASS-T™ DIGITAL AUDIO AMPLIFIER DRIVER
USING DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY
Technical Information
Revision 4.0 – July 2003
General Description
The TA2021B is a 25W (4Ω) continuous average per channel Class-T Digital Audio Power Amplifier IC
using Tripath’s proprietary Digital Power Processing (DPP
TM
) technology. Class-T amplifiers offer both
the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
Applications
DVD Receivers
Mini/Micro Component Systems
Computer / PC Multimedia
Cable Set-Top Products
Televisions
Battery Powered Systems
Features
Class-T architecture
Single Supply Operation
“Audiophile” Quality Sound
0.05% THD+N @ 13W 4Ω
0.1% THD+N @15.5W 4Ω
0.1% IHF-IM @ 1W 4Ω
High Power
25W @ 4Ω, 10% THD+N, V
DD
=14.6V
23.5W @ 4Ω, 10% THD+N, V
DD
=14.2V
14W @ 8Ω, 10% THD+N, V
DD
=14.2V
High Efficiency
88% @ 13.5W 8Ω
81% @ 25W 4Ω
Dynamic Range = 100 dB
Mute and Sleep inputs
Turn-on & turn-off pop suppression
Over-current protection
Over-temperature protection
Bridged outputs
36-pin PSOP “Slug-Up” package
Benefits
Fully integrated solution with internal FETs
Easier to design-in than Class-D
Dramatically improves efficiency versus Class-AB
amplifiers
Signal fidelity equal to high quality linear
amplifiers
High dynamic range compatible with digital media
such as CD and DVD, and internet audio
Typical Performance
THD+N vs Output Power
10
5
2
THD+N (%)
1
0.5
0.2
0.1
RL=4Ω
RL=8Ω
VDD=14.2V
Av=12V/V
BW=22-22kHz
0.05
0.02
0.01
600m
1
2
3
4
5 6 7 89
20
Output Power (W)
1
TA2021B – 4.0/07.03
Tri path Technol og y, I nc. - Techni cal I nformati on
Absolute maximum ratings
(Note 1)
SYMBOL
V
DD
V5
SLEEP
MUTE
T
STORE
T
A
T
J
Supply Voltage
Input Section Supply Voltage
SLEEP Input Voltage
MUTE Input Voltage
Storage Temperature Range
Operating Free-air Temperature Range
Junction Temperature
PARAMETER
Value
16
6.0
-0.3 to 6.0
-0.3 to V5+0.3
-40 to 150
-40 to 85
150
UNITS
V
V
V
V
°C
°C
°C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. See the
table below for Operating Conditions.
Note 2: Human body model, 100pF discharged through a 1.5KΩ resistor.
Note 3: Machine model, 220pF discharged through all pins.
Operating Conditions
(Note 4)
SYMBOL
V
DD
V
IH
V
IL
Supply Voltage
High-level Input Voltage (MUTE, SLEEP)
Low-level Input Voltage (MUTE, SLEEP)
PARAMETER
MIN.
8.5
3.5
1
TYP.
14.2
MAX.
14.6
UNITS
V
V
V
Note 4: Recommended Operating Conditions indicate conditions for which the device is functional. See
Electrical Characteristics for guaranteed specific performance limits.
Thermal Characteristics
SYMBOL
θ
JC
θ
JA
PARAMETER
Junction-to-case Thermal Resistance
Junction-to-ambient Thermal Resistance (still air)
VALUE UNITS
2.5
50
°
C/W
°
C/W
2
TA2021B – 3.0/04.03
Tri path Technol og y, I nc. - Techni cal I nformati on
Electrical Characteristics
(Notes 6, 7)
See Test/Application Circuit. Unless otherwise specified, V
DD
= 14.2V, f = 1kHz, Measurement
Bandwidth = 22kHz, R
L
= 4Ω, T
A
= 25
°C.
SYMBOL
P
O
PARAMETER
Output Power
(Continuous Average/Channel)
CONDITIONS
THD+N = 0.1%
THD+N = 10%
P
O
Output Power (V
DD
=14.6V)
(Continuous Average/Channel)
THD+N = 0.1%
THD+N = 10%
I
DD,MUTE
I
DD, SLEEP
I
q
THD + N
IHF-IM
SNR
CS
PSRR
η
V
OFFSET
V
OH
V
OL
e
OUT
Mute Supply Current
Sleep Supply Current
Quiescent Current
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
Power Supply Rejection Ratio
Power Efficiency
Output Offset Voltage
High-level output voltage
(FAULT & OVERLOADB)
Low-level output voltage
(FAULT & OVERLOADB)
Output Noise Voltage
MUTE = V
IH
SLEEP = V
IH
V
IN
= 0 V
P
O
= 10W/Channel
19kHz, 20kHz, 1:1 (IHF)
A-Weighted, P
OUT
= 25W, R
L
= 4Ω
0dBr = 1W, R
L
= 4Ω, f = 1 kHz
Vripple = 100mV
P
OUT
= 13.5W/Channel, R
L
= 8Ω
No Load, MUTE = Logic low
3.5
1
A-Weighted, input AC grounded
100
74
60
R
L
= 4Ω
R
L
= 8Ω
R
L
= 4Ω
R
L
= 8Ω
R
L
= 4Ω
R
L
= 8Ω
R
L
= 4Ω
R
L
= 8Ω
MIN.
TYP.
15.5
9
23.5
14
16.5
9.5
25
14.8
5.5
0.25
64
0.035
0.1
100
80
80
88
50
150
0.3
7
2
75
MAX.
UNITS
W
W
W
W
W
W
W
W
mA
mA
mA
%
%
dB
dB
dB
%
mV
V
V
µV
Note 6:
Note 7:
Minimum and maximum limits are guaranteed but may not be 100% tested.
For operation in ambient temperatures greater than 25°C, the device must be de-rated based on the
maximum junction temperature and the thermal resistance determined by the mounting technique.
3
TA2021B – 3.0/04.03
Tri path Technol og y, I nc. - Techni cal I nformati on
Pin Description
Pin
2, 3
Function
DCAP2, DCAP1
Description
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
Digital 5VDC, Analog 5VDC
Analog Ground
4, 9
5, 8,
17
6
7
10, 14
11, 15
12
16
18
19
20, 35
22
24, 27;
31, 28
25, 26,
29, 30
13, 21,
23, 32,
34
33
36
1
V5D, V5A
AGND1, AGND2,
AGND3
REF
OVERLOADB
OAOUT1, OAOUT2
INV1, INV2
MUTE
BIASCAP
SLEEP
FAULT
PGND2, PGND1
DGND
OUTP2 & OUTM2;
OUTP1 & OUTM1
VDD2, VDD2
VDD1, VDD1
NC
VDDA
CPUMP
5VGEN
Internal reference voltage; approximately 1.0 VDC.
A logic low output indicates the input signal has overloaded the amplifier.
Input stage output pins.
Single-ended inputs. Inputs are a “virtual” ground of an inverting op-amp with
approximately 2.4VDC bias.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
Input stage bias voltage (approximately 2.4VDC).
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Grounds (high current)
Digital Ground
Bridged outputs
Supply pins for high current H-bridges.
Not connected. Not bonded internally.
Supply pin for analog section.
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
TA2021B Pinout
36-pin Slug-Up SOP Package
(Top View)
CPUMP
PGND1
NC
VDDA
NC
OUTP1
VDD1
VDD1
OUTM1
OUTM2
VDD2
VDD2
OUTP2
NC
DGND
NC
PGND2
FAULT
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
+5VGEN
DCAP2
DCAP1
V5D
AGND1
REF
OVERLOADB
AGND2
V5A
OAOUT1
INV1
MUTE
NC
OAOUT2
INV2
BIASCAP
AGND3
SLEEP
4
TA2021B – 3.0/04.03
Tri path Technol og y, I nc. - Techni cal I nformati on
Application / Test Circuit
TA2021B
C
I
2.2uF
+
OAOUT1
10
R
F
20KΩ
INV1
11
VDD1
31
VDD1 (pin 29,30)
L
o
D
H
10uH, 2A
OUTP1
D
O
(Pin 35)
R
I
20KΩ
C
A
0.1uF
(Pin 8)
5V
BIASCAP
16
5V
Processing
&
Modulation
PGND1
VDD1
(Pin 35)
VDD1 (pin 29,30)
L
o
D
H
10uH, 2A
OUTM1
D
O
*C
o
0.47uF
C
Z
0.47uF
C
DO
0.1uF
R
Z
10Ω, 1/2W
R
L
4Ω or *8Ω
28
*C
o
0.47uF
MUTE
12
PGND1
(Pin 35)
FAULT
OVERLOADB
19
OAOUT2
14
R
F
20KΩ
INV2
15
7
VDD2
C
I
2.2uF
+
R
I
20KΩ
24
VDD2 (pin 25,26)
L
o
D
H
10uH, 2A
OUTP2
D
O
6
(Pin 8)
R
REF
8.25KΩ, 1%
REF
Processing
&
Modulation
PGND2
VDD2
(Pin 20)
(Pin 20)
VDD2 (pin 25,26)
L
o
D
H
10uH, 2A
OUTM2
D
O
*C
o
0.47uF
C
Z
0.47uF
C
DO
0.1uF
3
+12V
1M
Ω
0.1uF
C
D
0.1uF
DCAP1
27
R
Z
*C
o
0.47uF 10Ω, 1/2W
R
L
4Ω or *8Ω
2
18
4
DCAP2
PGND2
SLEEP
CPUMP
36
(Pin 20)
+
V5D
AGND1
V5A
AGND2
AGND3
5V
C
S
0.1uF
To Pin 1
VDDA
DGND
+5VGEN
VDD1
VDD1
33
22
1
30
29
C
P
1uF
C
S
0.1uF
C
S
0.1uF
To Pins 4,9
5
9
C
S
0.1uF
8
17
PGND1
35
C
SW
0.1uF
+
VDD (14.2V)
C
SW
180uF, 16V
13
21
23
32
34
VDD2
NC
VDD2
PGND2
25
26
20
C
SW
0.1uF
+
C
SW
180uF, 16V
Note: Analog and Digital/Power Grounds must
be connected locally at the TA2021
Analog Ground
Digital/Power Ground
All Diodes Motorola MBRS130T3
* Use C
o
= 0.22µF and C
z
= 0.22µF for 8 Ohm loads
5
TA2021B – 3.0/04.03
Microchip MCU
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