IS61LP6436A
IS61LP6432A
64K x 32, 64K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP package
• Power-down snooze mode
• Power Supply:
+3.3V V
dd
+3.3V or 2.5V V
ddq
(I/O)
• Lead-free available
®
Long-term Support
World Class Quality
MAY 2017
DESCRIPTION
The
ISSI
IS61LP6432A/36A is a high-speed synchronous
static RAM designed to provide a burstable, high-perfor-
mance memory for high speed networking and communica-
tion applications. The IS61LP6432A is organized as 64K
words by 32 bits and the IS61LP6436A is organized as 64K
words by 36 bits. Fabricated with
ISSI
's advanced CMOS
technology, the device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be writ-
ten.
BW1 controls DQa, BW2 controls DQb, BW3
controls
DQc, BW4 controls DQd, conditioned by BWE being LOW.
A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
-166
3.5
6
166
-133
4
7.5
133
Units
ns
ns
MHz
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. C1
05/22/2017
1
IS61LP6436A
IS61LP6432A
BLOCK DIAGRAM
MODE
CLK
CLK
Q0
A0
A0'
®
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World Class Quality
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1
A1'
64K x 32
64K x 36
MEMORY ARRAY
14
16
A15-A0
16
D
Q
ADDRESS
REGISTER
CE
CLK
x32/x36
x32/x36
GW
BWE
BW4
DQd
BYTE WRITE
REGISTERS
CLK
D
Q
BW3
DQc
Q
BYTE WRITE
REGISTERS
CLK
D
BW2
DQb
BYTE WRITE
REGISTERS
CLK
D
Q
BW1
DQa
Q
BYTE WRITE
REGISTERS
CLK
D
CE
CE2
CE2
D
Q
4
ENABLE
REGISTER
CE
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
x32/x36
OE
DQ[31:0]
DQ[35:0]
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc.
Rev. C1
05/22/2017
IS61LP6436A
IS61LP6432A
PIN CONFIGURATION
100-Pin TQFP
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
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DQPc
DQc1
DQc2
VDDQ
VSS
DQc3
DQc4
DQc5
DQc6
VSS
VDDQ
DQc7
DQc8
NC
VDD
NC
VSS
DQd1
DQd2
VDDQ
VSS
DQd3
DQd4
DQd5
DQd6
VSS
VDDQ
DQd7
DQd8
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb8
DQb7
VDDQ
VSS
DQb6
DQb5
DQb4
DQb3
VSS
VDDQ
DQb2
DQb1
VSS
NC
VDD
ZZ
DQa8
DQa7
VDDQ
VSS
DQa6
DQa5
DQa4
DQa3
VSS
VDDQ
DQa2
DQa1
DQPa
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE, CE2,
CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
V
dd
+3.3V Power Supply
Vss
Ground
V
ddq
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
DQPa-DQPd Parity Data I/O
A2-A15
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
Integrated Silicon Solution, Inc.
Rev. C1
05/22/2017
MODE
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
NC
64K x 36
3
IS61LP6436A
IS61LP6432A
PIN CONFIGURATION
100-Pin TQFP
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
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World Class Quality
NC
DQc1
DQc2
VDDQ
VSS
DQc3
DQc4
DQc5
DQc6
VSS
VDDQ
DQc7
DQc8
NC
VDD
NC
VSS
DQd1
DQd2
VDDQ
VSS
DQd3
DQd4
DQd5
DQd6
VSS
VDDQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VDDQ
VSS
DQb6
DQb5
DQb4
DQb3
VSS
VDDQ
DQb2
DQb1
VSS
NC
VDD
ZZ
DQa8
DQa7
VDDQ
VSS
DQa6
DQa5
DQa4
DQa3
VSS
VDDQ
DQa2
DQa1
NC
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE, CE2,
CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
V
dd
+3.3V Power Supply
Vss
Ground
V
ddq
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
A2-A15
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
MODE
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
NC
64K x 32
4
Integrated Silicon Solution, Inc.
Rev. C1
05/22/2017
IS61LP6436A
IS61LP6432A
TRUTH TABLE
(1-8)
OPERATION
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
ADDRESS
CE
None
H
None
L
None
L
None
L
None
L
None
X
External
L
External
L
External
L
External
L
External
L
Next
X
Next
X
Next
H
Next
H
Next
X
Next
H
Current
X
Current
X
Current
H
Current
H
Current
X
Current
H
CE2
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC ADV
L
X
X
X
X
X
L
X
L
X
X
X
X
X
X
X
L
X
L
X
L
X
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
®
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World Class Quality
WRITE OE
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
H
L
X
H
L
H
H
H
L
H
H
H
L
H
H
L
X
L
X
H
L
H
H
H
L
H
H
L
X
L
X
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-d) and
BWE are LOW or GW is LOW. WRITE
= H for all
BWx, BWE, GW HIGH.
3.
BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s
and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are avail-
able on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and
BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
BWa
X
H
L
L
X
BWb
X
H
H
L
X
BWc
X
H
H
L
X
BWd
X
H
H
L
X
5
Integrated Silicon Solution, Inc.
Rev. C1
05/22/2017
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