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PCI 9080 Data Sheet

version 0.93

February 28, 1997

Website/FTP Site:

http://www.plxtech.com

Email:

apps@plxtech.com

Phone:

408-774-9060

FAX:

408-774-1269

PLX Technology, Inc., 390 Potrero Ave., Sunnyvale, CA, 94086, Phone: 408-774-9060, Fax: 408-774-2169, Web: www.plxtech.com. PLX retains the

right to make changes to these specifications at any time, without notice. Products may have minor variations to this specification known as

errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.

PLX

Technology, Inc., 1997.

TABLE OF CONTENTS

1. GENERAL DESCRIPTION .......................................................................................................................................... 1

1.1 APPLICATIONS FOR THE PCI 9080...................................................................................................................... 2

1.1.1 PCI Adapter Cards ........................................................................................................................................... 2

1.1.2 Embedded Systems ......................................................................................................................................... 2

1.2 MAJOR FEATURES ............................................................................................................................................... 3

1.3 COMPATIBILITY OF PCI 9080 WITH PCI 9060, 9060ES, AND 9060SD ................................................................ 4

1.3.1 Pin Compatibility............................................................................................................................................... 4

1.3.2 Register Compatibility....................................................................................................................................... 4

1.4 COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080 .............................................................. 5

2. BUS OPERATION ....................................................................................................................................................... 6

2.1 PCI BUS CYCLES .................................................................................................................................................. 6

2.1.1 PCI Target Command Codes............................................................................................................................ 6

2.1.2 PCI Master Command Codes ........................................................................................................................... 6

2.1.2.1 DMA Master Command Codes.................................................................................................................................... 6

2.1.2.2 Direct Local to PCI Command Codes.......................................................................................................................... 6

2.2 LOCAL BUS CYCLES ............................................................................................................................................ 7

2.2.1 Local Bus Direct Master.................................................................................................................................... 7

2.2.2 Local Bus Direct Slave...................................................................................................................................... 7

2.2.2.1 Ready/Wait State Control ........................................................................................................................................... 7

2.2.2.2 Burst Mode and Continuous Burst Mode (BTERM “Burst Terminate” Mode)................................................................. 7

2.2.2.2.1 Burst Mode .......................................................................................................................................................... 7

2.2.2.2.2 Continuous Burst Mode (BTERM# “Burst Terminate” Mode) ................................................................................. 7

2.2.2.2.3 Partial Lword Accesses ........................................................................................................................................ 7

2.2.2.3 Recovery States.......................................................................................................................................................... 8

2.2.2.4 Local Bus Read Accesses........................................................................................................................................... 8

2.2.2.5 Local Bus Write Accesses........................................................................................................................................... 8

2.2.2.6 Direct Slave Write Accesses—8- and 16-Bit Buses ..................................................................................................... 8

2.2.2.7 Local Bus Data Parity ................................................................................................................................................. 8

2.2.2.8 Local Bus Little/Big Endian ......................................................................................................................................... 8

2.2.2.8.1 32 Bit Local Bus—Big Endian Mode ..................................................................................................................... 8

2.2.2.8.2 16 Bit Local Bus—Big Endian Mode ..................................................................................................................... 8

2.2.2.8.3 8 Bit Local Bus—Big Endian Mode ....................................................................................................................... 9

PLX Technology, Inc., 1997

Page ii

Version 0.93

TABLE OF CONTENTS

3. FUNCTIONAL DESCRIPTION................................................................................................................................... 10

3.1 RESET ................................................................................................................................................................. 10

3.1.1 PCI Bus Input RST# ....................................................................................................................................... 10

3.1.2 Local Bus Input LRESETi# ............................................................................................................................. 10

3.1.3 Local Bus Output LRESETo# ......................................................................................................................... 10

3.1.4 Software Reset............................................................................................................................................... 10

3.2 PCI 9080 INITIALIZATION.................................................................................................................................... 10

3.2.1 EEPROM Initialization..................................................................................................................................... 10

3.2.2 Local Initialization ........................................................................................................................................... 10

3.3 EEPROM.............................................................................................................................................................. 10

3.3.1 Short EEPROM Load ..................................................................................................................................... 11

3.3.2 Long EEPROM Load ...................................................................................................................................... 11

3.3.3 Extra Long EEPROM Load............................................................................................................................. 13

3.3.4 Recommended EEPROMs ............................................................................................................................. 13

3.4 INTERNAL REGISTER ACCESS ......................................................................................................................... 13

3.4.1 PCI Bus Access to Internal Registers ............................................................................................................. 13

3.4.2 Local Bus Access to Internal Registers ........................................................................................................... 14

3.5 DIRECT DATA TRANSFER MODES .................................................................................................................... 14

3.5.1 Direct Master Operation (Local Master to PCI Target)..................................................................................... 15

3.5.1.1 Decode ..................................................................................................................................................................... 15

3.5.1.2 FIFOs ....................................................................................................................................................................... 15

3.5.1.3 Memory Access ........................................................................................................................................................ 15

3.5.1.4 IO/CFG Access......................................................................................................................................................... 15

3.5.1.5 I/O ............................................................................................................................................................................ 16

3.5.1.6 CFG (PCI Configuration Type 0 or Type 1 Cycles) .................................................................................................... 16

3.5.1.7 Direct Bus Master Lock ............................................................................................................................................. 16

3.5.1.8 Master/Target Abort .................................................................................................................................................. 16

3.5.1.9 Write and Invalidate.................................................................................................................................................. 16

3.5.2 Direct Slave Operation (PCI Master to Local Bus Access) .............................................................................. 18

3.5.2.1 PCI to Local Address Mapping .................................................................................................................................. 18

3.5.2.1.1 Byte Enables...................................................................................................................................................... 18

3.5.2.1.2 Local Bus Initialization Software ......................................................................................................................... 19

3.5.2.1.3 PCI Initialization Software .................................................................................................................................. 19

3.5.2.2 Deadlock and BREQo ............................................................................................................................................... 21

3.5.2.2.1 Backoff .............................................................................................................................................................. 21

3.5.2.2.2 Software/Hardware Solution for Systems without Backoff Capability................................................................... 22

3.5.2.2.3 Software Solutions to Deadlock .......................................................................................................................... 22

PLX Technology, Inc., 1997

Page iii

Version 0.93

TABLE OF CONTENTS

3.5.2.3 Direct Slave Lock...................................................................................................................................................... 22

3.5.3 Direct Slave Priority ........................................................................................................................................ 22

3.6 DMA OPERATION................................................................................................................................................ 23

3.6.1 Non-Chaining Mode DMA ............................................................................................................................... 23

3.6.2 Chaining Mode DMA....................................................................................................................................... 24

3.6.3 DMA Data Transfers....................................................................................................................................... 25

3.6.3.1 Local to PCI Bus DMA Transfer ................................................................................................................................ 25

3.6.3.2 PCI to Local Bus DMA Transfer ................................................................................................................................ 26

3.6.3.3 Unaligned Transfers.................................................................................................................................................. 26

3.6.4 Demand Mode DMA ....................................................................................................................................... 26

3.6.5 DMA Priority ................................................................................................................................................... 27

3.6.6 DMA Arbitration .............................................................................................................................................. 27

3.6.6.1 End of Transfer (EOT0# or EOT1#) Input.................................................................................................................. 27

3.6.6.2 Local Latency and Pause Timers .............................................................................................................................. 27

3.7 BREQ INPUT........................................................................................................................................................ 27

3.8 DOORBELL REGISTERS..................................................................................................................................... 27

3.9 MAILBOX REGISTERS ........................................................................................................................................ 27

3.10 INTERRUPTS..................................................................................................................................................... 28

3.10.1 PCI Interrupts (INTA#) .................................................................................................................................. 28

3.10.1.1 Local Interrupt Input................................................................................................................................................ 28

3.10.1.2 Master/Target Abort Interrupt .................................................................................................................................. 28

3.10.2 Local Interrupts (LINTo#) .............................................................................................................................. 29

3.10.2.1 Local to PCI Doorbell Interrupt ................................................................................................................................ 29

3.10.2.2 PCI to Local Doorbell Interrupt ................................................................................................................................ 29

3.10.2.3 Built In Self Test Interrupt (BIST)............................................................................................................................. 29

3.10.2.4 DMA Channel 0/1 Interrupts .................................................................................................................................... 29

3.10.3 PCI SERR# (PCI NMI).................................................................................................................................. 30

3.10.4 Local LSERR# (Local NMI) ........................................................................................................................... 30

3.11 I

0 COMPATIBLE MESSAGE UNIT.................................................................................................................... 30

3.11.1 Inbound Messages ....................................................................................................................................... 30

3.11.2 Outbound Messages..................................................................................................................................... 31

3.11.3 I

O Pointer Management .............................................................................................................................. 31

3.11.4 Inbound Free List FIFO................................................................................................................................. 32

3.11.5 Inbound Post List FIFO................................................................................................................................. 34

3.11.6 Outbound Post List FIFO .............................................................................................................................. 34

3.11.7 Outbound Free List FIFO.............................................................................................................................. 34

PLX Technology, Inc., 1997

Page iv

Version 0.93

TABLE OF CONTENTS

4. REGISTERS .............................................................................................................................................................. 36

4.1 NEW REGISTER DEFINITIONS SUMMARY........................................................................................................ 36

4.1.1 Register Differences between PCI 9080 and PCI 9060, PCI 9060ES, and PCI 9060SD .................................. 37

4.2 REGISTER ADDRESS MAPPING ........................................................................................................................ 43

4.2.1 PCI Configuration Registers............................................................................................................................ 43

4.2.2 Local Configuration Registers ......................................................................................................................... 44

4.2.3 Runtime Registers .......................................................................................................................................... 45

4.2.4 DMA Registers ............................................................................................................................................... 46

4.2.5 Messaging Queue Registers........................................................................................................................... 47

4.3 PCI CONFIGURATION REGISTERS ................................................................................................................... 48

4.3.1 (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register ........................................................................... 48

4.3.1.1 (PCICR; PCI:04h, LOC:04h) PCI Command Register................................................................................................ 48

4.3.2 (PCISR; PCI:06h, LOC:06h) PCI Status Register............................................................................................ 49

4.3.3 (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register.................................................................................. 49

4.3.4 (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register ...................................................................... 50

4.3.5 (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register....................................................................... 50

4.3.6 (PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register............................................................................. 50

4.3.7 (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register .............................................................................. 51

4.3.8 (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register ........................................................... 51

4.3.9 (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses

to Local, Runtime, and DMA Registers .................................................................................................................... 52

4.3.10 (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses

to Local, Runtime, and DMA Registers .................................................................................................................... 52

4.3.11 (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses

to Local Address Space 0........................................................................................................................................ 53

4.3.12 (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses

to Local Address Space 1........................................................................................................................................ 54

4.3.13 (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register.......................................................................... 54

4.3.14 (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register.......................................................................... 54

4.3.15 (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer................................................................................. 55

4.3.16 (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID ........................................................................... 55

4.3.17 (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID .......................................................................................... 55

4.3.18 (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Register .......................................................... 55

4.3.19 (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Register.............................................................................. 55

4.3.20 (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register............................................................................... 56

4.3.21 (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register .................................................................................. 56

4.3.22 (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register ................................................................................... 56

PLX Technology, Inc., 1997

Page v

Version 0.93

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