Integrated
Circuit
Systems, Inc.
ICS1524A
Dual Output Phase Controlled SSTL_3/PECL Clock Generator
General Description
Features
Wide input frequency range
• 8 kHz to 100 MHz
250 MHz balanced PECL differential outputs
150 MHz single-ended SSTL_3 clock outputs
Dynamic Phase Adjust (DPA) for DPACLK
outputs
• Software controlled phase adjustment
• 360
o
Adjustment down to 1/64 clock
increments
External or internal loop filter selection
Uses 3.3 VDC Inputs are 5 volt tolerant.
I
2
C-bus serial interface runs at either low speed
(100 kHz) or high speed (400 kHz).
Hardware and Software PLL Lock detection
The
ICS1524A
is a low-cost, very high-performance •
frequency generator and phase controlled clock synthe-
sizer. It is perfectly suited to phase controlled clock
•
synthesis and distribution as well as line-locked and
•
genlocked applications.
•
The
ICS1524A
offers two channels of clock phase con-
trolled outputs; CLK and DPACLK. These two output
channels have both 250 MHz PECL differential and 150
MHz SSTL_3 single-ended output pins. The CLK output
channel has a fixed phase relationship to the PLL’s input
•
and the DPACLK uses the Dynamic Phase Adjust cir-
•
cuitry to allow control of the clock phase relative to input
•
signal.
Optionally, the CLK outputs can operate at half the clock
rate and phase aligned with the DPACLK channel, en-
abling deMUXing of multiplexed analog-to-digital
converters. The FUNC pin provides either the regener-
ated input from the phase-locked loop (PLL) divider
chain output or a re-synchronized and sharpened input
HSYNC.
The advanced PLL uses either its internal program-
mable feedback divider or an external divider and is
programmed by a standard I
2
C-bus™ serial interface.
•
Applications
•
•
•
Generic Frequency Synthesis
LCD Monitors and Projectors
Genlocking Multiple Video Systems
Block Diagram
Loop
Filter
Pin Configuration
VDDD
VSSD
SDA
SCL
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
HSYNC
OSC
I
2
C
DPACLK
DPACLK+/-
FUNC
24 Pin 300-mil SOIC
I C-bus is a trademark of Philips Corporation.
ICS1524A Rev F 05/13/10
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
2
ICS1524A
CLK
CLK+/-
IREF
CLK+
(PECL)
CLK–
(PECL)
DPACLK+ (PECL)
DPACLK– (PECL)
VSSQ
VDDQ
DPACLK (SSTL)
CLK
(SSTL)
FUNC
(SSTL)
LOCK/REF (SSTL)
I
2
CADR
ICS1524A
Document Revision History
Rev A
ICS1523 Rev T Datasheet used as a starting template
New Block Diagram substituted for old 1523 one
Removed reference to CLK / 2 Functionality
Created a set of clock outputs that bypass the DPA
External PDEN is now the IN-SEL MUX control bit
Text descriptions changed to support new 1524 block diagram
Rev B
Replaced page 15 “Layout Guidelines”
Replaced SIOC Package diagram on page 22
“Advanced Status” removed
Redrew front page graphics for clairity
Rev C
Corrected Chip Revision and Chip Version values on page 5
Changed Title on Page 1
Minor format changes to pages 8 and 21
Corrected pin names on page 10
Rev D
Miscellaneous updates to Block Diagram on page 3
Changed reference from “Phase Detector” to “Charge Pump”. Pages 4-7, 10
ICS1524A Rev F 05/13/10
2
Block Diagram
Osc_Div
Reg 0x7:0-6
PDEN
Reg 0x0:0
LOCK/REF
EnDLS
Reg 0:7
PDEN
EnPLS
Reg 0:6
Ref_Pol
Reg 0x0:2
PD_Pol
Reg 0x0:1
In_Sel
Reg 0x7:7
Fbk_Pol
Reg 0x0:3
PLL_LOCK
REG 12:1
DPA_LOCK
REG 12:0
PFD
Reg 0x1:0-2
Fill_Sel
Reg 0x4:7
Fbk_Sel
Reg 0x0:4
POST
SCALER
PSD
Reg 0x1:4-5
Out_Scl
Reg 0x6:6-7
Divider
3
DPA_OS
Reg 0x4:0-5
DPACLK
OE_Tck
Reg 0x6:1
DPACLK+
DPACLK-
OE_Pck
Reg 0x6:0
CLK
OE_T2
Reg 0x6:3
CLK+
FBD
Reg 0x2:0-7
FBD
DPA_Res
Reg 0x3:0-3
Reg 0x5:0-1
Func_Sel
Reg 0x0:5
MUX
Ck2_Inv
Reg 6:5
CLK-
OE_P2
Reg 0x6:2
ICS1524A Rev F 05/13/10
ICS1524A
OE_F
Reg 0x6:4
ICS1524A
Pin Descriptions
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P I N NA M E
VDDD
VSSD
S DA
SCL
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
V D DA
VSSA
OSC
I CADR
LOCK/REF
FUNC
CLK
D PAC L K
VDDQ
VSSQ
D PAC L K –
D PAC L K +
CLK–
CLK+
IREF
2
TYPE
PWR
PWR
IN/OUT
IN
IN
IN
IN
IN
IN
PWR
PWR
IN
IN
SSTL
SSTL
SSTL
SSTL
PWR
PWR
PECL
PECL
PECL
PECL
IN
DESCRIPTION
Digital supply
Digital ground
Serial data
Serial clock
C h a rg e P u m p
External feedback
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
I C address
Lock indicator/reference
Function output
P i xe l c l o c k t
DPA Delayed Clock
Output driver supply
Output driver ground
DPA Delayed PECL clock -
DPA Delayed PECL clock +
PECL clock -
PECL clock +
Reference current
2
COMMENTS
3.3V to digital sections
Ground for digital sections
I
2
C-bus
1
I
2
C-bus
1
S u s p e n d s c h a rg e p u m p
1
External divider input to P F D
1
Clock input to PLL
1
External PLL loop filter
External PLL loop filter return
3.3V for analog circuitry
Ground for analog circuitry
I n p u t f r o m c r y s t a l o s c i l l a t o r p a c k a g e
1, 2
C h i p I
2
C a d d r e s s s e l e c t
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
Displays PLL or DPA lock or REF input
SSTL_3 selectable HSYNC output
Non-Delayed SSTL_3 Clock
DPA Delayed SSTL_3 Clock
3.3V VDD for output drivers
Ground for output drivers
DPA Delayed Inverted PECL Clock Open drain.
DPA Delayed PECL Clock
Non-Delayed Inverted PECL Clock
Non-Delayed PECL Clock
Reference current for PECL outputs
Open drain.
Open drain.
Open drain.
Notes:
1. These LVTTL inputs are 5 V-tolerant.
2. Connect to ground if unused.
ICS1524A Rev F 05/13/10
4
ICS1524A
I
2
C Register Map Summary
Register
Index
0h
Name
Input Control
Access
R/W
Bit Name
PDen
PD_Pol
Ref_Pol
Fbk_Pol
Fbk_Sel
Func_Sel
EnPLS
EnDLS
1h
Loop Control
R/W*
PFD0-2
Reserved
PSD0-1
Reserved
2h
3h
FdBk Div 0
FdBk Div 1
R/W*
R/W*
FBD0-7
FBD8-11
Reserved
4h
DPA Offset
R/W
DPA_OS0-5
Reserved
Fil_Sel
5h
DPA Control
R / W ** DPA_Res0-1
Metal_Rev
6h
Output Enables
R/W
OE_Pck
OE_Tck
OE_P2
OE_T2
OE_F
Ck2_Inv
Out_Scl
7h
Osc_Div
R/W
Osc_Div 0-6
In-Sel
8h
Reset
Write
DPA
PLL
10h
11h
12h
Chip Ver
Chip Rev
Rd_Reg
Read
Read
Read
Chip Ver
Chip Rev
DPA_Lock
PLL_Lock
Reserved
Bit #
0
1
2
3
4
5
6
7
0-2
3
4-5
6-7
0-7
0-3
4-7
0-5
6
7
0-1
2-7
0
1
2
3
4
5
6-7
0-6
7
0-3
4-7
0-7
0-7
0
1
2-7
Reset
Value
1
0
0
0
0
0
1
0
0
0
0
0
FF
F
0
0
0
1
3
0
1
1
1
1
1
0
0
0
1
x
x
18
01
N/A
N/A
0
Charge Pump Enable
Charge Pump Enable Polarity
External Reference Polarity
External Feedback Polarity
External Feedback Select
Function Out Select
(0=Positive Edge, 1=Negative Edge)
(0=Positive Edge, 1=Negative Edge)
(0=Internal Feedback, 1=External)
(0=Recovered HSYNC, 1=Input HSYNC)
(0=Disable 1=Enable)
(0=Disable 1=Enable)
Description
(0=Disable 1=Enable)
Enable PLL Lock/Ref Status Output
Enable DPA Lock/Ref Status Output
Charge Pump Gain
Reserved
Post-Scaler Divider
Reserved
PLL FeedBack Divider LSBs (bits 0-7) *
PLL Feedback Divider MSBs (bits 8-11) *
Reserved
Dynamic Phase Aligner Offset
Reserved
Loop Filter Select
DPA Resolution
(0 = /2, 1 = /4, 2 = /8, 3 = /16)
(0=External, 1=Internal)
(0=16 delay elements, 1=32, 2=Reserved, 3=64)
Metal Mask Revision Number
Output Enable for PECL DPACLK
Output Enable for STTL_3 DPACLK
Output Enable for PECL CLK
Output Enable for STTL_3 CLK
Output Enable for STTL_3 FUNC
( 0=High Z, 1=Enabled)
( 0=High Z, 1=Enabled)
( 0=High Z, 1=Enabled)
( 0=High Z, 1=Enabled)
( 0=High Z, 1=Enabled)
Select non-delayed CLK (1) or DPA delayed CLK/2 (0) on CLKx pins
SSTL DPACLK (Pin 17) Scaler (0 = ÷1, 1 = ÷2, 2 = ÷4, 3 = ÷8)
Osc Divider modulus
RESERVED
Writing xA hex resets DPA and loads working register 5
Writing 5x hex resets PLL and loads working registers 1-3
Chip Version 17 hex
Chip Revision C2 hex
DPA Lock Status
PLL Lock Status
Reserved
(0=Unlocked, 1=Locked)
(0=Unlocked, 1=Locked)
* Identifies double-buffered registers. Working registers are loaded during software PLL reset.
** Identifies double-buffered register. Working registers are loaded during software DPA reset.
ICS1524A Rev F 05/13/10
5
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