Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> ISPGAL22V10AV-5LNNI

ISPGAL22V10AV-5LNNI: 产品描述SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD; 产品类别可编程逻辑器件可编程逻辑; 文件大小523KB，共20页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

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ISPGAL22V10AV-5LNNI概述

SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD

ISPGAL22V10AV-5LNNI规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Lattice(莱迪斯)
零件包装代码	QFN
包装说明	5 X 5 MM, LEAD FREE, QFN-32
针数	32
Reach Compliance Code	unknown
ECCN代码	EAR99
最大时钟频率	143 MHz
JESD-30 代码	S-XQCC-N32
JESD-609代码	e3
长度	5 mm
湿度敏感等级	1
专用输入次数	11
I/O 线路数量	10
端子数量	32
组织	11 DEDICATED INPUTS, 10 I/O
输出函数	MACROCELL
封装主体材料	UNSPECIFIED
封装代码	HVQCCN
封装形状	SQUARE
封装形式	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）	260
可编程逻辑类型	EE PLD
传播延迟	5 ns
认证状态	Not Qualified
座面最大高度	1 mm
最大供电电压	3.6 V
最小供电电压	3 V
标称供电电压	3.3 V
表面贴装	YES
技术	CMOS
端子面层	Matte Tin (Sn)
端子形式	NO LEAD
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	40
宽度	5 mm

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ispGAL™22V10AV/B/C Device Datasheet

June 2010

All Devices Discontinued!

Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in

this data sheet.

The original datasheet pages have not been modified and do not reflect those changes.

Please refer to the table below for reference PCN and current product status.

Product Line

ispGAL22V10AV

ispGAL22V10AB

Ordering Part Number

ispGAL22V10AV-23LS

ispGAL22V10AV-23LSN

ispGAL22V10AV-5LS

ispGAL22V10AV-5LSN

ispGAL22V10AV-75LS

ispGAL22V10AV-75LSN

ispGAL22V10AV-5LSI

ispGAL22V10AV-5LSNI

ispGAL22V10AV-75LSI

ispGAL22V10AV-75LSNI

ispGAL22V10AV-28LJ

ispGAL22V10AV-5LJ

ispGAL22V10AV-75LJ

ispGAL22V10AV-5LJI

ispGAL22V10AV-75LJI

ispGAL22V10AB-23LS

ispGAL22V10AB-5LS

ispGAL22V10AB-75LS

ispGAL22V10AB-5LSI

ispGAL22V10AB-75LSI

ispGAL22V10AB-28LJ

ispGAL22V10AB-5LJ

ispGAL22V10AB-75LJ

ispGAL22V10AB-5LJI

ispGAL22V10AB-75LJI

Product Status

Reference PCN

Discontinued

PCN#09-10

Discontinued

PCN#09-10

5555 N.E. Moore Ct.

Hillsboro, Oregon 97124-6421 Phone (503) 268-8000

Internet: http://www.latticesemi.com

FAX (503) 268-8347

Lattice Semiconductor

ispGAL22V10AV/B/C Data Sheet

ispGAL Architecture

Output Logic Macrocell (OLMC)

The ispGAL22V10A has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs

have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve

product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen

product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional

product-term dedicated to output enable control.

The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or

registered mode. This allows each output to be individually conﬁgured as either active high or active low.

D LL

C DE

TI CE

Figure 2. Output Logic Macrocell

The ispGAL22V10A has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset

(SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to

zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on

the rising edge of the next clock pulse after this product term is asserted.

NOTE: The AR and SP product terms will force the Q output of the ﬂip-ﬂop into the same state regardless of the

polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a

high or low at the output pin, depending on the pin polarity chosen.

4 TO 1

MUX

CLK

2 TO 1

MUX

Output Logic Macrocell Conﬁgurations

Each of the Macrocells of the ispGAL22V10A has two primary functional modes: registered, and combinatorial I/O.

The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic com-

piler. Each of these two primary modes, and the bit settings required to enable them, are described below and on

the following page.

Registered

In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-

type ﬂip-ﬂop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive

either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for

each OLMC, and can therefore be deﬁned by a logic equation. The D ﬂip-ﬂop’s /Q output is fed back into the AND

array, with both the true and complement of the feedback available as inputs to the AND array.

ISPGAL22V10AV-5LNNI相似产品对比

	ISPGAL22V10AV-5LNNI	ISPGAL22V10AC-75LNI	ISPGAL22V10AV-23LN	FP5548-222-GT	ISPGAL22V10AV-75LN	ISPGAL22V10AV-5LNN	ISPGAL22V10AB-5LN	ISPGAL22V10AV-75LNN	ISPGAL22V10AB-5LJI	ISPGAL22V10AV-5LJI
描述	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD	Fixed Resistor, Metal Film, 0.25W, 2200ohm, 250V, 2% +/-Tol, 100ppm/Cel,	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD	SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD
Reach Compliance Code	unknown	not_compliant	not_compliant	compliant	not_compliant	unknown	not_compliant	unknown	unknown	not_compliant
端子数量	32	32	32	2	32	32	32	32	28	28
封装形式	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Axial	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER	CHIP CARRIER
技术	CMOS	CMOS	CMOS	METAL FILM	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
是否Rohs认证	符合	不符合	不符合	-	不符合	符合	不符合	符合	不符合	不符合
厂商名称	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	-	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)
零件包装代码	QFN	QFN	QFN	-	QFN	QFN	QFN	QFN	QLCC	QLCC
包装说明	5 X 5 MM, LEAD FREE, QFN-32	5 X 5 MM, QFN-32	QFN-32	-	QFN-32	5 X 5 MM, LEAD FREE, QFN-32	QFN-32	5 X 5 MM, LEAD FREE, QFN-32	PLASTIC, LCC-28	PLASTIC, LCC-28
针数	32	32	32	-	32	32	32	32	28	28
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	-	EAR99	EAR99	EAR99
最大时钟频率	143 MHz	100 MHz	303 MHz	-	100 MHz	143 MHz	143 MHz	100 MHz	143 MHz	143 MHz
JESD-30 代码	S-XQCC-N32	S-XQCC-N32	S-XQCC-N32	-	S-XQCC-N32	S-XQCC-N32	S-XQCC-N32	S-XQCC-N32	S-PQCC-J28	S-PQCC-J28
JESD-609代码	e3	e0	e0	-	e0	e3	e0	e3	e0	e0
长度	5 mm	5 mm	5 mm	-	5 mm	5 mm	5 mm	5 mm	11.5062 mm	11.5062 mm
湿度敏感等级	1	1	1	-	1	1	1	1	1	1
专用输入次数	11	11	11	-	11	11	11	11	11	11
I/O 线路数量	10	10	10	-	10	10	10	10	10	10
组织	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	-	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O
输出函数	MACROCELL	MACROCELL	MACROCELL	-	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	-	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	HVQCCN	HVQCCN	HVQCCN	-	HVQCCN	HVQCCN	HVQCCN	HVQCCN	QCCJ	QCCJ
封装形状	SQUARE	SQUARE	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
峰值回流温度（摄氏度）	260	240	240	-	240	260	240	260	225	225
可编程逻辑类型	EE PLD	EE PLD	EE PLD	-	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
传播延迟	5 ns	7.5 ns	2.3 ns	-	7.5 ns	5 ns	5 ns	7.5 ns	5 ns	5 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1 mm	1 mm	1 mm	-	1 mm	1 mm	1 mm	1 mm	4.57 mm	4.57 mm
最大供电电压	3.6 V	1.95 V	3.6 V	-	3.6 V	3.6 V	2.7 V	3.6 V	2.7 V	3.6 V
最小供电电压	3 V	1.65 V	3 V	-	3 V	3 V	2.3 V	3 V	2.3 V	3 V
标称供电电压	3.3 V	1.8 V	3.3 V	-	3.3 V	3.3 V	2.5 V	3.3 V	2.5 V	3.3 V
表面贴装	YES	YES	YES	-	YES	YES	YES	YES	YES	YES
端子面层	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	-	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
端子形式	NO LEAD	NO LEAD	NO LEAD	-	NO LEAD	NO LEAD	NO LEAD	NO LEAD	J BEND	J BEND
端子节距	0.5 mm	0.5 mm	0.5 mm	-	0.5 mm	0.5 mm	0.5 mm	0.5 mm	1.27 mm	1.27 mm
端子位置	QUAD	QUAD	QUAD	-	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
处于峰值回流温度下的最长时间	40	30	30	-	30	40	30	40	30	30
宽度	5 mm	5 mm	5 mm	-	5 mm	5 mm	5 mm	5 mm	11.5062 mm	11.5062 mm
架构	-	PAL-TYPE	PAL-TYPE	-	PAL-TYPE	-	PAL-TYPE	-	PAL-TYPE	PAL-TYPE
输入次数	-	22	22	-	22	-	22	-	22	22
输出次数	-	10	10	-	10	-	10	-	10	10
产品条款数	-	132	132	-	132	-	132	-	132	132
封装等效代码	-	LCC32(UNSPEC)	LCC32(UNSPEC)	-	LCC32(UNSPEC)	-	LCC32(UNSPEC)	-	LDCC28,.5SQ	LDCC28,.5SQ
电源	-	1.8 V	3.3 V	-	3.3 V	-	2.5 V	-	2.5 V	3.3 V

ISPGAL22V10AV-5LNNI

ISPGAL22V10AV-5LNNI在线购买

ISPGAL22V10AV-5LNNI概述

ISPGAL22V10AV-5LNNI规格参数

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ISPGAL22V10AV-5LNNI相似产品对比

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