solutions optimized for synchronous buck applications
to offer high current, high efficiency, and high power
density performance. Packaged in Vishay’s proprietary
4.5 mm x 3.5 mm MLP package, SiC521 and SiC521A
enable voltage regulator designs to deliver up to 30 A
continuous current per phase.
The
internal
power
MOSFETs
utilize
Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC521 and SiC521A incorporate an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, and zero current detect to
improve light load efficiency. The drivers are also
compatible with a wide range of PWM controllers, support
tri-state PWM, and 3.3 V (SiC521A) / 5 V (SiC521) PWM
logic.
FEATURES
• Thermally enhanced PowerPAK
®
MLP4535-22L
package
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 30 A continuous current, 40 A at 10 ms peak
current
• 95 % peak efficiency
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 12 V input stage
• 3.3 V (SiC521A) / 5 V (SiC521) PWM logic with tri-state and
hold-off
• Zero current detect control for light load efficiency
improvement
• Low PWM propagation delay (< 20 ns)
• Under voltage lockout for V
CIN
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for CPU, GPU, and memory
• Synchronous buck converters
• DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
5V
V
DRV
V
IN
V
IN
BOOT
PHASE
V
SWH
V
CIN
ZCD_EN#
PWM
controller
Gate
driver
V
OUT
PWM
Fig. 1 - SiC521 and SiC521A Typical Application Diagram
C
GND
G
L
P
GND
S15-0170-Rev. B, 09-Feb-15
Document Number: 62989
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC521, SiC521A
www.vishay.com
PINOUT CONFIGURATION
P
GND
P
GND
P
GND
V
IN
V
IN
V
IN
Vishay Siliconix
11
10
9
8
7
6
V
SWH
12
V
SWH
13
V
SWH
14
V
SWH
15
V
SWH
16
24
GL
26
P
GND
25
V
IN
5
4
3
PHASE
BOOT
C
GND
V
CIN
ZCD_EN#
23
C
GND
2
1
17
P
GND
18
P
GND
19
GL
20
P
GND
21
V
DRV
22
PWM
Fig. 2 - SiC521 and SiC521A Pin Configuration
PIN DESCRIPTION
PIN NUMBER
1
2
3, 23
4
5
6 to 8, 25
9 to 11, 17, 18, 20, 26
12 to 16
19, 24
21
22
NAME
ZCD_EN#
V
CIN
C
GND
BOOT
PHASE
V
IN
P
GND
V
SWH
GL
V
DRV
PWM
ZCD control. Active low
Supply voltage for internal logic circuitry
Analog ground for the driver IC
High-side driver bootstrap voltage
Return path of high-side gate driver
Power stage input voltage. Drain of high-side MOSFET
Power ground
Switch node of the power stage
Low-side gate signal
Supply voltage for internal gate driver
PWM control input
FUNCTION
ORDERING INFORMATION
PART NUMBER
SiC521CD-T1-GE3
SiC521ACD-T1-GE3
SiC521ADB and SiC521DB
PACKAGE
PowerPAK
®
MLP4535-22L
MARKING CODE
SiC521
SiC521A
Reference board
5 V PWM optimized
3.3 V PWM optimized
S15-0170-Rev. B, 09-Feb-15
Document Number: 62989
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC521, SiC521A
www.vishay.com
Vishay Siliconix
CONDITIONS
V
IN
V
CIN
V
DRV
V
SWH
V
BOOT
V
BOOT- PHASE
LIMIT
-0.3 to +25
-0.3 to +7
-0.3 to +7
-0.3 to +25
-8 to +30
32
38
-0.3 to +7
-0.3 to +8
-0.3 to V
CIN
+ 0.3
f
S
= 300 kHz, V
IN
= 12 V, V
OUT
= 1.8 V
f
S
= 1 MHz, V
IN
= 12 V, V
OUT
= 1.8 V
T
J
T
A
T
stg
Human body model, JESD22-A114
Charged device model, JESD22-C101
30
25
150
-40 to +125
-65 to +150
3000
1000
V
°C
A
V
UNIT
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
Input Voltage
Control Logic Supply Voltage
Drive Supply Voltage
Switch Node (DC voltage)
Switch Node (AC
voltage)
(1)
BOOT Voltage (DC voltage)
BOOT Voltage (AC voltage)
(2)
BOOT to PHASE (DC voltage)
BOOT to PHASE (AC voltage)
All Logic Inputs and Outputs
(PWM and ZCD_EN#)
Output Current, I
OUT(AV) (4)
Max. Operating Junction Temperature
Ambient Temperature
Storage Temperature
Electrostatic Discharge Protection
(3)
Note
(1)
The specification values indicated “AC” is V
SWH
to P
GND
, -8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.
(2)
The specification value indicates “AC voltage” is V
BOOT
to P
GND
, 36 V (< 50 ns) max.
(3)
The specification value indicates “AC voltage” is V
BOOT
to V
PHASE
, 8 V (< 20 ns) max.
(4)
Output current rated with testing evaluation board at T = 25 °C with natural convection cooling. The rating is limited by the peak evaluation
A
board temperature, T
J
= 150 °C, and varies depending on the operating conditions and PCB layout. This rating may be changed with different
application settings.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Input Voltage (V
IN
)
Drive Supply Voltage (V
DRV
)
Control Logic Supply Voltage (V
CIN
)
BOOT to PHASE (V
BOOT-PHASE
, DC voltage)
Thermal Resistance from Junction to PCB
Thermal Resistance from Junction to Case
MINIMUM
4.5
4.5
4.5
4
-
-
TYPICAL
-
5
5
4.5
5
2.5
MAXIMUM
18
5.5
5.5
5.5
-
-
°C/W
V
UNIT
S15-0170-Rev. B, 09-Feb-15
Document Number: 62989
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC521, SiC521A
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
(ZCD_EN# = 5 V, V
IN
= 12 V, V
DRV
and V
CIN
= 5 V, T
A
= 25 °C)
PARAMETER
POWER SUPPLY
Control Logic Supply Current
I
VCIN
no switching, V
PWM
= FLOAT
f
S
= 300 kHz, D = 0.1
f
S
= 300 kHz, D = 0.1
f
S
= 1 MHz, D = 0.1
no switching, V
PWM
= FLOAT
I
F
= 2 mA
-
-
-
-
-
-
3.4
0.72
-
0.9
3.1
-
-
V
PWM
= 5 V
V
PWM
= 0 V
-
-
2.2
0.72
-
0.9
1.95
-
-
V
PWM
= 3.3 V
V
PWM
= 0 V
-
-
-
-
-
No load, see fig. 4
-
-
-
30
Input logic high
Input logic low
V
CIN
rising, on threshold
V
CIN
falling, off threshold
2
-
-
2.7
-
300
300
8
30
50
-
3.7
0.9
2.3
1.15
3.35
225
325
-
-
2.45
0.9
1.8
1.15
2.2
225
275
-
-
20
150
20
10
20
10
-
-
-
3.7
3.1
575
-
-
15
-
-
0.4
4.0
1.1
-
1.38
3.6
-
mV
V
HYS_TRI_F
I
PWM
-
350
-350
2.7
1.1
-
1.38
2.45
-
mV
V
HYS_TRI_F
I
PWM
-
225
-225
-
-
-
-
-
-
-
-
0.8
4.1
-
-
V
ns
μA
μA
μA
mA
μA
V
SYMBOL
TEST CONDITION
LIMITS
MIN.
TYP.
MAX.
UNIT
Drive Supply Current
BOOTSTRAP SUPPLY
Bootstrap Diode Forward Voltage
PWM CONTROL INPUT (SiC521)
Rising Threshold
Falling Threshold
Tri-state Voltage
Tri-state Rising Threshold
Tri-state Falling Threshold
Tri-state Rising Threshold
Hysteresis
Tri-state Falling Threshold
Hysteresis
PWM Input Current
PWM CONTROL INPUT (SiC521A)
Rising Threshold
Falling Threshold
Tri-state Voltage
Tri-state Rising Threshold
Tri-state Falling Threshold
Tri-state Rising Threshold
Hysteresis
Tri-state Falling Threshold
Hysteresis
PWM Input Current
TIMING SPECIFICATIONS
Tri-State to GH/GL Rising
Propagation Delay
Tri-state Hold-Off Time
GH - Turn Off Propagation Delay
GH - Turn On Propagation Delay
(Dead time rising)
GL - Turn Off Propagation Delay
GL - Turn On Propagation Delay
(Dead time falling)
PWM Minimum On-Time
ZCD_EN# INPUT
ZCD_EN# Logic Input Voltage
PROTECTION
Under Voltage Lockout
Under Voltage Lockout Hysteresis
I
VDRV
V
F
V
TH_PWM_R
V
TH_PWM_F
V
TRI
V
TRI_TH_R
V
TRI_TH_F
V
HYS_TRI_R
V
PWM
= FLOAT
V
V
TH_PWM_R
V
TH_PWM_F
V
TRI
V
TRI_TH_R
V
TRI_TH_F
V
HYS_TRI_R
V
PWM
= FLOAT
V
t
PD_TRI_R
t
TSHO
t
PD_OFF_GH
t
PD_ON_GH
t
PD_OFF_GL
t
PD_ON_GL
t
PWM_ON_MIN
V
IH_ZCD_EN#
V
IL_ZCD_EN#
V
UVLO
V
UVLO_HYST
V
mV
Notes
(1)
Typical limits are established by characterization and are not production tested.
(2)
Guaranteed by design.
S15-0170-Rev. B, 09-Feb-15
Document Number: 62989
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC521, SiC521A
www.vishay.com
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V
PWM_TH_R
the low-side is turned OFF and the high-side is
turned ON. When PWM input is driven below V
PWM_TH_F
the
high-side is turned OFF and the low-side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC521 and
SiC521A to pull the PWM input into the tri-state region (see
definition of PWM logic and Tri-State, fig. 4). If the PWM
input stays in this region for the Tri-state Hold-Off Period,
t
TSHO
, both high-side and low-side MOSFETs are turned
OFF. The function allows the VR phase to be disabled
without negative output voltage swing caused by inductor
ringing and saves a Schottky diode clamp. The PWM and
tri-state regions are separated by hysteresis to prevent false
triggering. The SiC521A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC521 thresholds are compatible with 5 V logic.
Diode Emulation Mode (ZCD_EN#)
When ZCD_EN# pin is logic low and PWM signal switches
low, GL is forced ON (after normal BBM time). During this
time, it is under control of the ZCD (zero crossing detect)
comparator. If, after the internal blanking delay, the inductor
current becomes zero, the low-side is turned OFF. This
improves light load efficiency by avoiding discharge of
output capacitors. If PWM enters tri-state, then device will
go into normal tri-state mode after tri-state delay. The GL
output will be turned OFF regardless of Inductor current, this
is an alternative method of improving light load efficiency by
reducing switching losses.
Voltage Input (V
IN
)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Switch Node (V
SWH
and PHASE)
The switch node, V
SWH
, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node, V
SWH
. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 kΩ resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that V
CIN
goes to zero while V
IN
is still applied.
Ground Connections (C
GND
and P
GND
)
P
GND
(power ground) should be externally connected to
C
GND
(control signal ground). The layout of the printed circuit
board should be such that the inductance separating C
GND
and P
GND
is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V.
Control and Drive Supply Voltage Input (V
DRV
, V
CIN
)
V
CIN
is the bias supply for the gate drive control IC. V
DRV
is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC521 and SiC521A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high-side and low-side
MOSFETs are not turned ON at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the
MOSFET turning ON from tuning ON until the other
MOSFET's gate voltage is sufficiently low (< 1 V). Built in
delays also ensure that one power MOSFET is completely
OFF, before the other can be turned ON. This feature helps
to adjust dead time as gate transitions change with respect
to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC521 and
SiC521A also incorporate logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 kΩ
resistor is connected between GH and PHASE to provide a
discharge path for the HS MOSFET.
Vishay Siliconix
S15-0170-Rev. B, 09-Feb-15
Document Number: 62989
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
这是一份协作蓝图，旨在通过 Arm 的汽车创新生态系统，应对集成复杂性并打造可扩展解决方案。 未来出行的变革不仅在颠覆汽车行业，更在不断加剧汽车的复杂性。由人工智能 (AI) 驱动的驾驶体验、车云互联能力与云原生开发，正在重塑汽车的设计、制造与体验。 汽车中先进软件与 AI 能力的快速集成和持续部署，为日益复杂的系统带来了诸多挑战：如何确保无缝集成、实时性能、功能安全与网络安全？此外，协...[详细]
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
