Low Skew, 1-to-16 Differential-to-
LVDS, Clock Distribution Chip
ICS8516I
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS8516I is a low skew, high performance 1-
to-16 Differential-to-LVDS Clock Distribution Chip
HiPerClockS™
and a member of the HiPerClockS™ family of High
Perfor mance Clock Solutions from IDT. The
ICS8516I CLK, nCLK pair can accept any differ-
ential input levels and translates them to 3.3V LVDS output
levels. Utilizing Low Voltage Differential Signaling (LVDS), the
ICS8516I provides a low power, low noise, point-to-point solu-
tion for distributing clock signals over controlled impedances
of 100Ω.
F
EATURES
•
Sixteen Differential LVDS outputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Maximum output frequency: 700MHz
•
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
•
Translates any single-ended input signal to LVDS
with resistor bias on nCLK input
•
Multiple output enable inputs for disabling unused
outputs in reduced fanout applications
•
LVDS compatible
•
Output skew: 65ps (maximum)
•
Part-to-part skew: 550ps (maximum)
•
Propagation delay: 2.4ns (maximum)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
Dual output enable inputs allow the ICS8516I to be used in a
1-to-16 or 1-to-8 input/output mode. Guaranteed output and
part-to-part skew specifications make the ICS8516I ideal for
those applications demanding well defined performance and
repeatability.
B
LOCK
D
IAGRAM
CLK
nCLK
P
IN
A
SSIGNMENT
Q9
nQ9
Q8
nQ8
GND
OE2
OE1
GND
nQ7
Q7
nQ6
Q6
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
V
DD
nQ5
Q5
nQ4
Q4
V
DD
GND
nQ3
Q3
nQ2
Q2
V
DD
48
47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
ICS8516I
36
35
34
33
32
31
30
29
28
27
26
25
V
DD
nQ10
Q10
nQ11
Q11
V
DD
GND
nQ12
Q12
nQ13
Q13
V
DD
OE1
OE2
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
nQ14
Q14
nQ15
Q15
GND
CLK
nCLK
GND
Q0
nQ0
Q1
nQ1
ICS8516I REVISION B SEPTEMBER 10, 2009
1
©2009
Integrated Device Technology, Inc.
ICS8516I Data Sheet
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6, 12,
25, 31, 36
2, 3
4, 5
7, 17, 20,
30, 41, 44
8, 9
10, 11
13, 14
15, 16
18
19
21, 22
23, 24
26, 27
28, 29
32, 33
34, 35
37, 38
39, 40
Name
V
DD
nQ5, Q5
nQ4, Q4
GND
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nCLK
CLK
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Q11, nQ11
Q10, nQ10
Q9, nQ9
Q8, nQ8
Power
Output
Output
Power
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pulldown
Type
Description
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inver ting differential clock input.
Non-inver ting differential clock input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15;
OE1 controls outputs Q0, nQ0 thru Q7, nQ7.
42, 43
OE2, OE1
Input
Pullup
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
45, 46
nQ7, Q7
Output
47, 48
nQ6, Q6
Output
Differential output pair. LVDS interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS8516I REVISION B SEPTEMBER 10, 2009
2
©2009
Integrated Device Technology, Inc.
ICS8516I Data Sheet
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Test Conditions
Minimum
Typical
4
51
51
4
Maximum
Units
pF
KΩ
KΩ
pF
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
O E1
0
1
0
1
OE2
0
0
1
1
Q0:Q7
Hi Z
ACTIVE
Hi Z
ACTIVE
nQ0:nQ7
Hi Z
ACTIVE
Hi Z
ACTIVE
Outputs
Q8:Q15
Hi Z
Hi Z
ACTIVE
ACTIVE
nQ8:nQ15
Hi Z
Hi Z
ACTIVE
ACTIVE
In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B.
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
Q0:Q15
nQ0:nQ15
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
ICS8516I REVISION B SEPTEMBER 10, 2009
3
©2009
Integrated Device Technology, Inc.
ICS8516I Data Sheet
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
47.9°C/W (0 lfpm)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Static Power Supply Current
R
L
= 100
Ω
No Load
Test Conditions
Minimum
3.135
Typical
3. 3
Maximum
3.465
185
80
Units
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE1, OE2
OE1, OE2
OE1, OE2
OE1, OE2
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Voltage
0.15
Common Mode Input Voltage;
V
CMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined ast V
IH
.
ICS8516I REVISION B SEPTEMBER 10, 2009
4
©2009
Integrated Device Technology, Inc.
ICS8516I Data Sheet
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
I
OZ
I
OFF
I
OSD
I
OS
/I
OSB
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
High Impedance Leakage Current
Power Off Leakage
Differential Output Shor t Circuit Current
Output Shor t Circuit Current
-10
-1
1.125
1.4
Test Conditions
Minimum
250
Typical
400
Maximum
600
50
1.6
50
+10
+1
-5.5
-12
Units
mV
mV
V
mV
µA
µA
mA
mA
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
1.6
2.0
Test Conditions
Minimum
Typical
Maximum
700
2. 4
65
550
Integration Range:
12kHz - 20MHz
20% to 80%
IJ 600MHz
50
45
148
600
55
5
5
Units
MHz
ns
ps
ps
fs
ps
%
ns
ns
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
odc
t
PZL
, t
PZH
t
PLZ
, t
PHZ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditons.“
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
ICS8516I REVISION B SEPTEMBER 10, 2009
5
©2009
Integrated Device Technology, Inc.
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