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SSTUH32864EC557

产品描述Registers 1.8V CONFIG REG
产品类别半导体    逻辑   
文件大小101KB,共21页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
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SSTUH32864EC557概述

Registers 1.8V CONFIG REG

SSTUH32864EC557规格参数

参数名称属性值
产品种类
Product Category
Registers
制造商
Manufacturer
NXP(恩智浦)
Logic TypeCMOS
Logic FamilySSTU
Number of Circuits1
Maximum Clock Frequency450 MHz
传播延迟时间
Propagation Delay Time
1.8 ns
High Level Output Current- 12 mA
Low Level Output Current12 mA
电源电压-最大
Supply Voltage - Max
1.9 V
最小工作温度
Minimum Operating Temperature
0 C
最大工作温度
Maximum Operating Temperature
+ 70 C
封装 / 箱体
Package / Case
SOT-536
系列
Packaging
Tray
高度
Height
1.2 mm
Input TypeSingle-Ended
长度
Length
13.6 mm
安装风格
Mounting Style
SMD/SMT
Number of Channels25
Number of Input Lines25
Number of Output Lines25
工作电源电压
Operating Supply Voltage
1.8 V
PolarityNon-Inverting
Reset TypeAsynchronous
工厂包装数量
Factory Pack Quantity
1425
电源电压-最小
Supply Voltage - Min
1.7 V
Triggering TypePositive-Edge/Negative-Edge
宽度
Width
5.6 mm

文档预览

下载PDF文档
SSTUH32864
1.8 V high output drive configurable registered buffer for
DDR2 RDIMM applications
Rev. 01 — 22 April 2005
Product data sheet
1. General description
The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed
for 1.7 V to 1.9 V V
DD
operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUH32864 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and un-driven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs
must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUH32864 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS
and CSR control and will force the outputs LOW. If the DCS-control functionality is not
desired, then the CSR input can be hardwired to ground, in which case the setup time
requirement for DCS would be the same as for the other Dn data inputs.
The SSTUH32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96)
package.

SSTUH32864EC557相似产品对比

SSTUH32864EC557 SSTUH32864EC518
描述 Registers 1.8V CONFIG REG Registers 1.8V CONFIG REG
产品种类
Product Category
Registers Registers
制造商
Manufacturer
NXP(恩智浦) NXP(恩智浦)
Logic Type CMOS CMOS
Logic Family SSTU SSTU
Number of Circuits 1 1
Maximum Clock Frequency 450 MHz 450 MHz
传播延迟时间
Propagation Delay Time
1.8 ns 1.8 ns
High Level Output Current - 12 mA - 12 mA
Low Level Output Current 12 mA 12 mA
电源电压-最大
Supply Voltage - Max
1.9 V 1.9 V
最小工作温度
Minimum Operating Temperature
0 C 0 C
最大工作温度
Maximum Operating Temperature
+ 70 C + 70 C
封装 / 箱体
Package / Case
SOT-536 SOT-536
系列
Packaging
Tray Reel
高度
Height
1.2 mm 1.2 mm
Input Type Single-Ended Single-Ended
长度
Length
13.6 mm 13.6 mm
安装风格
Mounting Style
SMD/SMT SMD/SMT
Number of Channels 25 25
Number of Input Lines 25 25
Number of Output Lines 25 25
工作电源电压
Operating Supply Voltage
1.8 V 1.8 V
Polarity Non-Inverting Non-Inverting
Reset Type Asynchronous Asynchronous
工厂包装数量
Factory Pack Quantity
1425 3500
电源电压-最小
Supply Voltage - Min
1.7 V 1.7 V
Triggering Type Positive-Edge/Negative-Edge Positive-Edge/Negative-Edge
宽度
Width
5.6 mm 5.6 mm
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