®
HSP43220
Data Sheet
October 10, 2008
FN2486.10
Decimating Digital Filter
The HSP43220 Decimating Digital Filter is a linear phase
low pass decimation filter which is optimized for filtering
narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220 offers a single chip
solution to signal processing applications which have
historically required several boards of ICs. This reduction in
component count results in faster development times as well
as reduction of hardware costs.
The HSP43220 is implemented as a two stage filter
structure. As seen in the block diagram, the first stage is a
high order decimation filter (HDF) which utilizes an efficient
sample rate reduction technique to obtain decimation up to
1024 through a coarse low-pass filtering process. The HDF
provides up to 96dB aliasing rejection in the signal pass
band. The second stage consists of a finite impulse
response (FIR) decimation filter structured as a transversal
FIR filter with up to 512 symmetric taps which can implement
filters with sharp transition regions. The FIR can perform
further decimation by up to 16 if required while preserving
the 96dB aliasing attenuation obtained by the HDF. The
combined total decimation capability is 16,384.
The HSP43220 accepts 16-bit parallel data in 2’s
complement format at sampling rates up to 33MSPS. It
provides a 16-bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several ICs to a common bus. The
HSP43220 also provides the capability to bypass either the
HDF or the FIR for additional flexibility.
Features
• Single Chip Narrow Band Filter with up to 96dB
Attenuation
• DC to 33MHz Clock Rate
• 16-Bit 2’s Complement Input
• 20-Bit Coefficients in FIR
• 24-Bit Extended Precision Output
• Programmable Decimation up to a Maximum of 16,384
• Standard 16-Bit Microprocessor Interface
• Filter Design Software Available DECIMATE™
• Up to 512 Taps
• Pb-Free Available (RoHS compliant)
Applications
• Very Narrow Band Filters
• Zoom Spectral Analysis
• Channelized Receivers
• Large Sample Rate Converter
Ordering Information
PART
NUMBER
HSP43220JC-25
PART
MARKING
HSP43220JC-25
TEMP.
RANGE
(°C)
0 to +70
0 to +70
0 to +70
0 to +70
PACKAGE
PKG.
DWG. #
84 Ld PLCC N84.1.15
84 Ld PLCC N84.1.15
(Pb-free)
84 Ld PLCC N84.1.15
84 Ld PLCC N84.1.15
(Pb-free)
HSP43220JC-25Z HSP43220JC-25Z
HSP43220JC-33
HSP43220JC-33
HSP43220JC-33Z HSP43220JC-33Z
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
NOTE: DECIMATE Software Development Tool (This software tool
may be downloaded from our internet site: www.intersil.com
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2004, 2008. All Rights Reserved
DECIMATE™ is a trademark of Intersil Corporation.
All other trademarks mentioned are the property of their respective owners.
HSP43220
Block Diagram
DECIMATION UP TO 1024
INPUT CLOCK
DATA INPUT
CONTROL AND COEFFICIENTS
HIGH ORDER
DECIMATION
FILTER
DECIMATION UP TO 16
FIR
DECIMATION
FILTER
FIR CLOCK
24
DATA OUT
DATA READY
16
16
Pinout
HSP43220
84 PLASTIC LEADED CHIP CARRIER (PLCC)
TOP VIEW
GND
DATA_IN 0
DATA_IN 1
DATA_IN 2
DATA_IN 3
DATA_IN 4
DATA_IN 5
DATA_IN 6
DATA_IN 7
DATA_IN 8
DATA_IN 9
DATA_IN 10
DATA_IN 11
DATA_IN 12
DATA_IN 13
DATA_IN 14
DATA_IN 15
V
CC
GND
CK_IN
V
CC
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
STARTOUT
V
CC
STARTIN
ASTARTIN
RESET
A1
A0
WR
CS
C_BUS 15
C_BUS 14
C_BUS 13
C_BUS 12
C_BUS 11
C_BUS 10
C_BUS 9
V
CC
GND
C_BUS 8
C_BUS 7
C_BUS 6
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
C_BUS 5
C_BUS 4
C_BUS 3
C_BUS 2
C_BUS 1
C_BUS 0
OUT_SELH
OUT_ENP
OUT_ENX
V
CC
GND
FIR_CK
V
CC
GND
DATA_RDY
DATA_OUT 23
DATA_OUT 22
DATA_OUT 21
DATA_OUT 20
DATA_OUT 19
DATA_OUT 18
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
GND
DATA_OUT 0
DATA_OUT 1
DATA_OUT 2
DATA_OUT 3
DATA_OUT 4
DATA_OUT 5
DATA_OUT 6
DATA_OUT 7
DATA_OUT 8
DATA_OUT 9
DATA_OUT 10
DATA_OUT 11
GND
V
CC
DATA_OUT 12
DATA_OUT 13
DATA_OUT 14
DATA_OUT 15
DATA_OUT 16
DATA_OUT 17
Pin Description
NAME
V
CC
GND
CK_IN
I
TYPE
The +5V power supply pins.
The device ground.
Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock
frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN
can be divided down from FIR_CK. CK_IN is a CMOS level signal.
Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the
rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal.
DESCRIPTION
FIR_CK
I
2
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October 10, 2008
HSP43220
Pin Description
NAME
DATA_IN0-15
TYPE
I
(Continued)
DESCRIPTION
Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a
synchronous fashion, and is latched on the rising edge of the CK_IN signal. The data bus is in 2's complement fractional
format. Bit 15 is the MSB.
Control Input Bus. This input bus is used to load all the filter parameters. The pins WR, CS and A0, A1 are used to select
the destination of the data on the Control bus and write the Control bus data into the appropriate register as selected by A0
and A1
Output Data Bus. This 24-Bit output port is used to provide the filtered result in 2's complement format. The upper 8 bits of
the output, DATA_OUT16-23 will provide extension or growth bits depending on the state of OUT_SELH and whether the
FIR has been put in bypass mode. Output bits DATA_OUT0-15 will provide bits 20 through 2-15 when the FIR is not
bypassed and will provide the bits 2-16 through 2-31 when the FIR is in bypass mode.
An active high output strobe that is synchronous with FIR_CK that indicates that the result of the just completed FIR cycle
is available on the data bus.
RESET is an asynchronous signal which requires that the input clocks CK_IN and FIR_CK are active when RESET is
asserted. RESET disables the clock divider and clears all of the internal data registers in the HDF. The FIR filter data path
is not initialized. The control register bits that are cleared are F_BYP, H_STAGES, and H_DRATE. The F_DIS bit is set. In
order to guarantee consistent operation of the part, the user must reset the DDF after power-up.
Write Strobe. WR is used for loading the internal registers of the HSP43220. When CS and WR are asserted, the rising edge of
WR will latch the C_BUS0-15 data into the register specified by A0 and A1.
Chip Select. The Chip Select input enables loading of the internal registers. When CS and WR are low, the A0 and A1 address
lines are decoded to determine the destination of the data on C_BUS0-15. The rising edge of WR then loads the appropriate
register as specified by A0 and A1.
Control Register Address. These lines are decoded to determine which control register is the destination for the data on
C_BUS0-15. Register loading is controlled by the A0 and A1, WR and CS inputs.
ASTARTIN is an asynchronous signal which is sampled on the rising edge of CK_IN. It is used to put the DDF in operational
mode. ASTARTIN is internally synchronized to CK_IN and is used to generate STARTOUT.
STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN. It is provided as an output for use
in multi-chip configurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of
CK_IN.
STARTIN is a Synchronous Input. A high to low transition of this signal is required to start the part. STARTIN is sampled on
the rising edge of CK_IN. This synchronous signal can be used to start single or multiple HSP43220's.
Output Select. The OUT_SELH input controls which bits are provided at output pins DATA_OUT16-23. A HIGH on this control
line selects bits 28 through 21 from the accumulator output. A LOW on this control line selects bits 2-16 through 2-23 from
the accumulator output. Processing is not interrupted by this pin.
Output Enable. The OUT_ENP input controls the state of the lower 16 bits of the output data bus, DATA_OUT0-15. A LOW on
this control line enables the lower 16 bits of the output bus. When OUT_ENP is HIGH, the output drivers are in the high
impedance state. Processing is not interrupted by this pin.
Output Enable. The OUT_ENX input controls the state of the upper 8 bits of the output data bus, DATA_OUT16-23. A LOW
on this control line enables the upper 8 bits of the output bus. When OUT_ENX is HIGH, the output drivers are in the high
impedance state. Processing is not interrupted by this pin.
C_BUS0-15
I
DATA_OUT
0-23
O
DATA_RDY
RESET
O
I
WR
CS
I
I
A0, A1
ASTARTIN
STARTOUT
I
I
O
STARTIN
OUT_SELH
I
I
OUT_ENP
I
OUT_ENX
I
The HDF
The first filter section is called the High Order Decimation Filter
(HDF) and is optimized to perform decimation by large factors.
It implements a low pass filter using only adders and delay
elements instead of a large number of multiplier/ accumulators
that would be required using a standard FIR filter.
The HDF is divided into 4 sections: the HDF filter section,
the clock divider, the control register logic and the start logic
(Figure 1).
Data Shifter
After being latched into the Input Register the data enters the
Data Shifter. The data is positioned at the output of the shifter
to prevent errors due to overflow occurring at the output of the
HDF. The number of bits to shift is controlled by H_GROWTH.
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HSP43220
Integrator Section
The data from the shifter goes to the Integrator section.
This is a cascade of 5 integrator (or accumulator) stages,
which implement a low pass filter. Each accumulator is
implemented as an adder followed by a register in the feed
forward path. The integrator is clocked by the sample clock,
CK_IN as shown in Figure 2. The bit width of each integrator
stage goes from 66 bits at the first integrator down to 26 bits
at the output of the fifth integrator. Bit truncation is performed
at each integrator stage because the data in the integrator
stages is being accumulated and thus is growing, therefore
the lower bits become insignificant, and can be truncated
without losing significant data.
There are three signals that control the integrator section;
they are H_STAGES, H_BYP and RESET. In Figure 2 these
control signals have been decoded and are labelled
INT_EN1 - INT_EN5. The order of the filter is loaded via the
A0-1
WR
CS
C_BUS
H_DRATE
CONTROL
REGISTER LOGIC
H_BYP
CLOCK
DIVIDER
ISTART
START
LOGIC
STARTOUT
CK_IN
RESET
control bus and is called H_STAGES. H_STAGES is
decoded to provide the enables for each integrator stage.
When a given integrator stage is selected, the feedback path
is enabled and the integrator accumulates the current data
sample with the previous sum. The integrator section can be
put in bypass mode by the H_BYP bit. When H_BYP or
RESET is asserted, the feedback paths in all integrator
stages are cleared.
Decimation Register
The output of the Integrator section is latched into the
Decimation Register by CK_DEC. The output of the
Decimation register is cleared when RESET is asserted. The
HDF decimation rate = H_DRATE +1, which is defined as
H
DEC
for convenience.
RESET
CK_IN ASTARTIN
STARTIN
6
H_GROWTH
5
INT_EN1-5
5
COMB_EN1-5
CK DEC
HDF FILTER SECTION
ISTART
H_GROWTH
6
DATA
IN 16
INPUT
REG
16
DATA
SHIFTER 66
INT_EN1-5
5
INTEGRATOR
DEC
REG 26
RESET
COMB_EN1-5
5
TO FIR
COMB FILTER
19
ROUND
16
REG
16
RESET
26
CK_IN
CK_DEC
TO FIR
FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE
0
MUX
MUX
0
MUX
0
MUX
0
MUX
0
FROM
SHIFTER
66
CK
IN
INT_EN5
INT_EN4
INT_EN3
INT_EN2
INT_EN1
TO
DECIMATION
REGISTER
26
∑
REG
63
∑
REG
53
∑
REG
43
∑
REG
35
∑
REG
FIGURE 2. INTEGRATOR
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FN2486.10
October 10, 2008
HSP43220
COMB_EN5
FROM
DECIMATION
REGISTER
RESET
26
CK_DEC
REG
B A-B
22
A
COMB_EN4
COMB_EN3
COMB_EN2
COMB_EN1
RESET
REG
B A-B
21
A
RESET
REG
19
B A-B
20
A
RESET
REG
B A-B
19
A
RESET
REG
B A-B
A
TO
ROUNDER
FIGURE 3. COMB FILTER
Comb Filter Section
The output of the Decimation Register is passed to the
Comb Filter Section. The Comb section consists of 5
cascaded Comb filters or differentiators. Each Comb filter
section calculates the difference between the current and
previous integrator output. Each Comb filter consists of a
register which is clocked by CK_DEC, followed by an
subtractor, where the subtractor calculates the difference
between the input and output of the register. Bit truncations
are done at each stage as shown in Figure 3. The first
stage bit width is 26 bits and the output of the fifth stage is
19 bits.
There are three signals that control the Comb Filter;
H_STAGES, H_BYP and RESET. In Figure 3 these control
signals are decoded as COMB_EN1 - COMB_EN5. The
order of the Comb filter is controlled by H_STAGES, which is
programmed over the control bus. H_BYP is used to put the
comb section in bypass mode. RESET causes the register
output in each Comb stage to be cleared. The H_ BYP and
RESET control pins, when asserted force the output of all
registers to zero so data is passed through the subtractor
unaltered. When the H_STAGES control bits enable a given
stage the output of the register is subtracted from the input.
It is important to note that the Comb filter section has a speed
limitation. The Input sampling rate divided by the decimation
factor in the HDF (CK_IN/H
DEC
) should not exceed 4MHz.
Violating this condition causes the output of the filter to be
incorrect. When the HDF is put in bypass mode this limitation
does not apply. Equation 2 describes the relationship between
F_TAPS, F_DRATE, H_DRATE, CK_IN and FIR_CK.
filter stage in the HDF section has a 16-bit integer portion
with a 3-bit fractional part in 2's complement format.
The rounding algorithm is as follows:
POSITIVE NUMBERS
Fractional Portion
≥
to 0.5
Fractional Portion < 0.5
NEGATIVE NUMBERS
Fractional Portion
≤
0.5
Fractional Portion > 0.5
Round-Up
Truncate
Round-Up
Truncate
The output of the rounder is latched into the HDF output
register with CK_DEC. CK_DEC is generated by the Clock
Divider section. The output of the register is cleared when
RESET is asserted.
Clock Divider and Control Logic
The clock divider divides CK_IN by the decimation factor
H
DEC
to produce CK_DEC. CK_DEC clocks the Decimation
Register, Comb Filter section, HDF output register. In the
FIR filter CK_DEC is used to indicate that a new data sample
is available for processing. The clock generator is cleared by
RESET and is not enabled until the DDF is started by an
internal start signal (see “Start Logic” on page 9).
The Control Register Logic enables the updating of the Control
registers which contain all of the filter parameter data. When
WR and CS are asserted, the control register addressed by bits
A0 and A1 is loaded with the data on the C_BUS.
Rounder
The filter accuracy is limited by the 16-bit data input. To
maintain the maximum accuracy, the output of the comb is
rounded to 16 bits.
The Rounder performs a symmetric round of the 19-bit
output of the last Comb stage. Symmetric rounding is done
to prevent the synthesis of a 0Hz spectral component by the
rounding process and thus causing a reduction in spurious
free dynamic range. Saturation logic is also provided to
prevent roll over from the largest positive value to the most
negative value after rounding. The output of the last comb
5
FN2486.10
October 10, 2008
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