Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> LFE2M100SE-5F900C

LFE2M100SE-5F900C: 产品描述FPGA - Field Programmable Gate Array 95K LUTs 416 S Ser Memory DSP 1.2V 5SPD; 产品类别可编程逻辑器件可编程逻辑; 文件大小16MB，共771页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com

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LFE2M100SE-5F900C概述

FPGA - Field Programmable Gate Array 95K LUTs 416 S Ser Memory DSP 1.2V 5SPD

LFE2M100SE-5F900C规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	Lattice(莱迪斯)
零件包装代码	BGA
包装说明	FPBGA-900
针数	900
Reach Compliance Code	compliant
ECCN代码	EAR99
Is Samacsys	N
最大时钟频率	311 MHz
CLB-Max的组合延迟	0.358 ns
JESD-30 代码	S-PBGA-B900
JESD-609代码	e0
长度	31 mm
湿度敏感等级	3
输入次数	416
逻辑单元数量	100000
输出次数	416
端子数量	900
最高工作温度	85 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA900,30X30,40
封装形状	SQUARE
封装形式	GRID ARRAY
峰值回流温度（摄氏度）	225
电源	1.2 V
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY
认证状态	Not Qualified
座面最大高度	2.6 mm
最大供电电压	1.26 V
最小供电电压	1.14 V
标称供电电压	1.2 V
表面贴装	YES
温度等级	OTHER
端子面层	Tin/Lead (Sn63Pb37)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
宽度	31 mm
Base Number Matches	1

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LatticeECP2/M Family Handbook

HB1003 Version 05.3, February 2012

LatticeECP2/M Family Handbook

Table of Contents

February 2012

Section I. LatticeECP2/M Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-2

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PFU Blocks ........................................................................................................................................................ 2-3

Slice .......................................................................................................................................................... 2-3

Modes of Operation................................................................................................................................... 2-5

Routing............................................................................................................................................................... 2-6

sysCLOCK Phase Locked Loops (GPLL/SPLL) ................................................................................................ 2-6

General Purpose PLL (GPLL) ................................................................................................................... 2-6

Standard PLL (SPLL) ................................................................................................................................ 2-7

Delay Locked Loops (DLL)................................................................................................................................. 2-8

DLLDELA Delay Block .............................................................................................................................. 2-9

PLL/DLL Cascading .................................................................................................................................. 2-9

GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only) .................................................. 2-10

Clock Dividers .................................................................................................................................................. 2-10

Clock Distribution Network ............................................................................................................................... 2-11

Primary Clock Sources............................................................................................................................ 2-11

Secondary Clock/Control Sources .......................................................................................................... 2-13

Edge Clock Sources................................................................................................................................ 2-14

Primary Clock Routing ............................................................................................................................ 2-15

Dynamic Clock Select (DCS) .................................................................................................................. 2-15

Secondary Clock/Control Routing ........................................................................................................... 2-15

Slice Clock Selection............................................................................................................................... 2-17

Edge Clock Routing ................................................................................................................................ 2-18

sysMEM Memory ............................................................................................................................................. 2-19

sysMEM Memory Block........................................................................................................................... 2-19

Bus Size Matching .................................................................................................................................. 2-19

RAM Initialization and ROM Operation ................................................................................................... 2-19

Memory Cascading ................................................................................................................................. 2-19

Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-19

Memory Core Reset ................................................................................................................................ 2-20

EBR Asynchronous Reset....................................................................................................................... 2-20

sysDSP™ Block ............................................................................................................................................... 2-21

sysDSP Block Approach Compared to General DSP ............................................................................. 2-21

sysDSP Block Capabilities ...................................................................................................................... 2-21

MULT sysDSP Element .......................................................................................................................... 2-23

MAC sysDSP Element ............................................................................................................................ 2-24

MULTADDSUB sysDSP Element ........................................................................................................... 2-25

MULTADDSUBSUM sysDSP Element ................................................................................................... 2-26

Clock, Clock Enable and Reset Resources ............................................................................................ 2-26

Signed and Unsigned with Different Widths............................................................................................ 2-27

OVERFLOW Flag from MAC .................................................................................................................. 2-27

IPexpress™............................................................................................................................................. 2-28

Optimized DSP Functions ................................................................................................................................ 2-28

Resources Available in the LatticeECP2/M Family ................................................................................. 2-28

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

LatticeECP2/M DSP Performance .......................................................................................................... 2-29

Programmable I/O Cells (PIC) ......................................................................................................................... 2-29

PIO ................................................................................................................................................................... 2-31

Input Register Block ................................................................................................................................ 2-31

Output Register Block ............................................................................................................................. 2-33

Tristate Register Block ............................................................................................................................ 2-35

Control Logic Block ................................................................................................................................. 2-35

DDR Memory Support...................................................................................................................................... 2-35

Left and Right Edges............................................................................................................................... 2-35

Bottom Edge ........................................................................................................................................... 2-35

Top Edge................................................................................................................................................. 2-36

DLL Calibrated DQS Delay Block ........................................................................................................... 2-37

Polarity Control Logic .............................................................................................................................. 2-39

DQSXFER............................................................................................................................................... 2-40

sysI/O Buffer .................................................................................................................................................... 2-40

sysI/O Buffer Banks ................................................................................................................................ 2-40

Typical sysI/O I/O Behavior During Power-up......................................................................................... 2-43

Supported sysI/O Standards ................................................................................................................... 2-43

Hot Socketing.......................................................................................................................................... 2-45

SERDES and PCS (Physical Coding Sublayer)............................................................................................... 2-46

SERDES Block........................................................................................................................................ 2-46

PCS......................................................................................................................................................... 2-47

SCI (SERDES Client Interface) Bus........................................................................................................ 2-47

IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-48

Device Configuration........................................................................................................................................ 2-48

Soft Error Detect (SED) Support ............................................................................................................. 2-48

External Resistor..................................................................................................................................... 2-49

On-Chip Oscillator................................................................................................................................... 2-49

Density Shifting ................................................................................................................................................ 2-49

DC and Switching Characteristics

Absolute Maximum Ratings

, ,

............................................................................................................................. 3-1

Recommended Operating Conditions ................................................................................................................ 3-1

Hot Socketing Specifications.............................................................................................................................. 3-2

ESD Performance .............................................................................................................................................. 3-2

DC Electrical Characteristics.............................................................................................................................. 3-3

LatticeECP2 Supply Current (Standby).............................................................................................................. 3-4

LatticeECP2M Supply Current (Standby)........................................................................................................... 3-5

LatticeECP2 Initialization Supply Current .......................................................................................................... 3-6

LatticeECP2M Initialization Supply Current ....................................................................................................... 3-7

SERDES Power Supply Requirements (LatticeECP2M Family Only) ............................................................... 3-8

SERDES Power (LatticeECP2M Family Only)................................................................................................... 3-8

sysI/O Recommended Operating Conditions..................................................................................................... 3-9

sysI/O Single-Ended DC Electrical Characteristics.......................................................................................... 3-10

sysI/O Differential Electrical Characteristics .................................................................................................... 3-11

LVDS....................................................................................................................................................... 3-11

Differential HSTL and SSTL.................................................................................................................... 3-11

LVDS25E ................................................................................................................................................ 3-12

LVCMOS33D .......................................................................................................................................... 3-12

BLVDS .................................................................................................................................................... 3-13

LVPECL .................................................................................................................................................. 3-14

RSDS ...................................................................................................................................................... 3-15

MLVDS.................................................................................................................................................... 3-16

Typical Building Block Function Performance.................................................................................................. 3-17

Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-17

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

Register-to-Register Performance .......................................................................................................... 3-17

Derating Timing Tables .................................................................................................................................... 3-18

LatticeECP2/M External Switching Characteristics.......................................................................................... 3-19

LatticeECP2/M Internal Switching Characteristics ........................................................................................... 3-28

Timing Diagrams .............................................................................................................................................. 3-30

LatticeECP2/M Family Timing Adders ............................................................................................................. 3-32

sysCLOCK GPLL Timing ................................................................................................................................. 3-35

sysCLOCK SPLL Timing.................................................................................................................................. 3-36

DLL Timing....................................................................................................................................................... 3-37

SERDES High-Speed Data Transmitter (LatticeECP2M Family Only) ............................................................ 3-38

SERDES High Speed Data Receiver (LatticeECP2M Family Only) ................................................................ 3-41

Input Data Jitter Tolerance...................................................................................................................... 3-41

SERDES External Reference Clock (LatticeECP2M Family Only) ......................................................... 3-43

SERDES Power-Down/Power-Up Specification .............................................................................................. 3-43

PCI Express Electrical and Timing Characteristics .......................................................................................... 3-44

AC and DC Characteristics ..................................................................................................................... 3-44

LatticeECP2/M sysCONFIG Port Timing Specifications .................................................................................. 3-46

JTAG Port Timing Specifications ..................................................................................................................... 3-50

Switching Test Conditions................................................................................................................................ 3-51

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-4

LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 .......................................................................... 4-5

LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 ........................................................................ 4-7

LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 ........................................................................ 4-9

LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 ............................................................... 4-11

LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100............................................ 4-13

Available Device Resources by Package, LatticeECP2................................................................................... 4-15

Available Device Resources by Package, LatticeECP2M................................................................................ 4-15

LatticeECP2 Power Supply and NC................................................................................................................. 4-16

LatticeECP2 Power Supply and NC (Cont.)..................................................................................................... 4-17

LatticeECP2M Power Supply and NC.............................................................................................................. 4-18

LatticeECP2M Power Supply and NC (Cont.).................................................................................................. 4-19

LatticeECP2M Power Supply and NC (Cont.).................................................................................................. 4-21

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP ........................................................... 4-22

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP......................................................... 4-26

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA .......................................................... 4-31

LFE2-20E/SE Logic Signal Connections: 256 fpBGA ...................................................................................... 4-39

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA ........................................................ 4-47

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA ........................................................ 4-60

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA ........................................................ 4-73

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA ........................................................ 4-91

LFE2-70E/SE Logic Signal Connections: 900 fpBGA .................................................................................... 4-109

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA ................................................ 4-134

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA .................................................. 4-141

LFE2M50E/SE Logic Signal Connections: 484 fpBGA .................................................................................. 4-153

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA .................................................. 4-167

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA .................................................. 4-184

LFE2M100E/SE Logic Signal Connections: 900 fpBGA ................................................................................ 4-206

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA .............................................. 4-231

Ordering Information

LatticeECP2 Part Number Description............................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

LatticeECP2 Standard Series Devices, Conventional Packaging............................................................. 5-2

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

LatticeECP2 Standard Series Devices, Lead-Free Packaging .......................................................................... 5-5

LatticeECP2 S-Series Devices, Conventional Packaging......................................................................... 5-8

LatticeECP2 S-Series Devices, Lead-Free Packaging ........................................................................... 5-11

LatticeECP2M Part Number Description.......................................................................................................... 5-14

Ordering Information ........................................................................................................................................ 5-14

LatticeECP2M Standard Series Devices, Conventional Packaging........................................................ 5-15

LatticeECP2M Standard Series Devices, Lead-Free Packaging ............................................................ 5-18

LatticeECP2M S-Series Devices, Lead-Free Packaging ........................................................................ 5-23

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

LatticeECP2/M Family Data Sheet Revision History

Revision History ................................................................................................................................................. 7-1

Section II. LatticeECP2/M Family Technical Notes

LatticeECP2M SERDES/PCS Usage Guide

Introduction to PCS ............................................................................................................................................ 8-1

Features ............................................................................................................................................................. 8-1

Supported Standards ......................................................................................................................................... 8-2

Architecture Overview ........................................................................................................................................ 8-2

PCS Quad ................................................................................................................................................. 8-2

PCS Quad and Channels.......................................................................................................................... 8-3

Per Channel PCS/FPGA Interface Ports................................................................................................... 8-4

Locating a PCS Quad ............................................................................................................................... 8-4

Detailed Channel Block Diagram .............................................................................................................. 8-4

SCI (SERDES Client Interface) Bus.......................................................................................................... 8-7

Using This Technical Note ........................................................................................................................ 8-7

SERDES/PCS .................................................................................................................................................... 8-7

I/O Definitions............................................................................................................................................ 8-9

SERDES/PCS Functional Description ............................................................................................................. 8-12

SERDES ................................................................................................................................................. 8-12

Reference Clock Usage .......................................................................................................................... 8-13

Transmit Data.......................................................................................................................................... 8-16

Receive Data........................................................................................................................................... 8-16

Configuration GUIs........................................................................................................................................... 8-27

Configuration File Description ................................................................................................................. 8-38

LatticeECP2M PCS in Gigabit Ethernet Mode ................................................................................................. 8-39

Gigabit Ethernet (1000BASE-X) Idle Insert............................................................................................. 8-39

Gigabit Ethernet Idle Insert and ff_correct_disp_ch[3:0] Signal Usage................................................... 8-39

LatticeECP2M PCS in PCI Express Mode ....................................................................................................... 8-39

PCS Loopback Modes ..................................................................................................................................... 8-41

Serial Loopback Mode ............................................................................................................................ 8-41

SERDES Parallel Loopback Mode.......................................................................................................... 8-41

PCS Parallel Loopback Mode ................................................................................................................. 8-41

FPGA Interface Clocks Usage ......................................................................................................................... 8-42

2-to-1 Gearing ......................................................................................................................................... 8-44

SERDES/PCS Block Latency........................................................................................................................... 8-49

SERDES Client Interface (SCI)........................................................................................................................ 8-50

Interrupts and Status............................................................................................................................... 8-52

SERDES Client Interface Application Example....................................................................................... 8-53

Dynamic Configuration of SERDES/PCS Quad...................................................................................... 8-54

SERDES Debug Capabilities .................................................................................................................. 8-54

Control Boxes and Buttons, Status Boxes and the Text Window ........................................................... 8-56

Other Design Considerations ........................................................................................................................... 8-56

LatticeECP2M-35 vs. All Other LatticeECP2M Devices.......................................................................... 8-56

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多点触控手机解析

多点触摸手机多点触控是系统可以同时响应操作者在屏幕上多点操作，多点触控手机分为电容式和电阻式，以iphone为代表的电容式屏幕手机，可以多点触控，但电容式手机受温度影响较大，已出现漂移现象。以N97为代表的电阻式屏幕手机，屏幕每次只能确认操作者的在一点的触控,iphone 则是3点以上触控多点触摸的定义传统的触控屏幕一次只能判断一个触控点，若同时有两个以上的点被触碰，就不能做出正确反应...[详细]
苹果首款折叠 iPhone 曝料：配自研 C2 基带芯片

8 月 25 日消息，彭博社的马克・古尔曼昨日（8 月 24 日）发布博文，曝料称苹果将于 2026 年推出其首款折叠手机（下文简称 iPhone Fold），一方面会明显减少屏幕折痕，另一方面将搭载其自研的 C2 基带芯片，并采用无 SIM 卡设计、Touch ID 解锁，测试机有黑、白两色。苹果为尽量减少折痕的视觉影响，决定将屏幕触控感应层由 on-cell 技术改为 in-cell 技术...[详细]
韩国机器人巨头WIRobotics推出人形机器人

近日，韩国机器人巨头 WIRobotics 在韩国科技大学机器人创新中心 (RIH) 推出了其首款通用人形机器人 ALLEX，其设计旨在利用其像人类一样对刺激做出反应的能力来处理多项任务，它拥有 15 个自由度 (DOF)，可以实现逼真的动作和复杂的交互。此外，ALLEX 还配备了从腰部到上身的重力补偿机制，能提供 40 N的指尖力。凭借这项创新，ALLEX 可以在不消耗过多能量或承受任何机械应...[详细]
小型计算机——加固边缘部署的实时数据分析

与云数据库相比，小型计算机是专门为网络边缘的去中心化坚固计算而构建的。通过将应用程序、分析和处理服务移动到更靠近数据生成源的位置，业务运营可以获得改进的实时计算应用程序性能。 l 从奔腾到酷睿i5的可扩展CPU性能 l 智能电源点火管理和CAN总线网络支持 l 无线局域网和广域网LTE连接 l 丰富的I/O可扩展性，包括PoE、PCI、PCIe、COM l 适用于宽工作温度和宽电压输入的坚固...[详细]
基于DIL的转向系统SOTIF场景开发分析

【摘要】为了提高智能网联汽车横向主动安全，将转向系统（EPS）的非预期功能安全场景识别和定义融入系统设计与开发环节。结合场景域分析、等价类和边界值技术，通过解构EPS相关车辆模型变体和横向运动场景，从EPS已知的运行场景中拓展出更多可能存在风险的工作场景。同时，利用基于半实物仿真的驾驶员在环系统（DIL），凭借其“人-车-环境”闭环的优势，使得更多未知风险场景转变为有效的已知场景，进而优化现有...[详细]
燃油车进入智能化拐点，电子电气架构“下放”

过去十年，燃油车的叙事始终是“衰退”与“替代”。在新能源汽车的攻势下，传统车企被迫在电动化的转型赛道上加速。但真正能延长燃油车生命力的，不是新的动力总成，而是智能化架构的“下放”。大众与小鹏联合开发的CEA区域控制电子电气架构，原本是为电动车设计的集中式计算系统，如今正被移植到燃油与混合动力车型。这不是一次简单的技术平移，而是对燃油车定义的重塑：它不再只是依赖机械性能的过渡产品...[详细]
直线模组中对联轴器有区分吗？

随着自动化设备的普及，作为自动化设备常用辅助设备的直线模组，也迎来了大好前景。特别是最近几年出现了很多小型设备厂家，在追求的生产效率和产品周转率的情况下，其机械设计生产模块化已经达到了整个产品设计的80%以上，以轻资产的模式运营和发展已经成为了众多新兴厂商的追求。直线模组的结构非常简单简单，而联轴器是其重要的配件，想必大家对联轴器也是非常熟悉的，主要用于丝杆加工端连接伺服电机，以此实现运动...[详细]

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