DATASHEET
ISL6731A, ISL6731B
Power Factor Correction Controllers
The ISL6731A and ISL6731B are active power factor
correction (PFC) controller ICs that use a boost topology. The
controllers are suitable for AC/DC power systems up to 2kW
and over the universal line input.
The ISL6731A and ISL6731B operate in Continuous Current
Mode (CCM). Accurate input current shaping is achieved with a
current error amplifier. A patent pending breakthrough
negative capacitance technology minimizes zero crossing
distortion and reduces the magnetic components size. The
small external components result in lower design cost without
sacrificing performance.
The internally clamped 12.5V gate driver delivers 1.5A peak
current to the external power MOSFET. The ISL6731A and
ISL6731B provide a highly reliable system that is fully
protected. Protection features include cycle-by-cycle
overcurrent, over power limit, over-temperature, input
brownout, output overvoltage and undervoltage protection.
The ISL6731A and ISL6731B provide excellent power
efficiency and transitions into a power saving skip mode
during light load conditions, thus improving efficiency
automatically. The ISL6731A and ISL6731B can be shut down
by pulling the FB pin below 0.5V or grounding the BO pin.
Two switching frequency options are provided. The ISL6731B
switches at 62kHz, and the ISL6731A switches at 124kHz.
FN8582
Rev 1.00
February 13, 2015
Features
• Reduced component size requirements
- Enables smaller, thinner AC/DC adapters
- Choke and cap size can be reduced
- Lower cost of materials
• Excellent power factor and THD over line and load
- CCM mode with negative capacitance generator for
smaller EMI filter and improved performance
- Built-in current amplifier with flexibility of gain change
• Better light-load efficiency
- Automatic pulse skipping with programmable threshold
- Programmable or automatic shutdown
• Highly reliable design
- Cycle-by-cycle current limit
- Input average power limit
- OVP and OTP protection
- Input brownout protection
• Small 14 Ld SOIC package
Applications
• Desktop computer AC/DC adaptor
• Laptop computer AC/DC adaptor
• TV AC/DC power supply
• AC/DC brick converters
Related Literature
•
AN1884,
"ISL6731AEVAL1Z and ISL6731BEVAL1Z: Boost
CCM PFC for 300W Universal Input Adaptors"
•
AN1885,
“ISL6731AEVAL2Z and ISL6731BEVAL2Z: High
Performance Boost CCM PFC Front End for Server Power
Applications”
V
LINE
V
I
100
+
V
OUT
95
90
EFFICIENCY (%)
85
80
75
70
65
60
0
20
40
60
OUTPUT POWER (%)
80
100
ISL6731A, NON-SKIP
ISL6731A, SKIP
VCC
ISEN
ICOMP
VIN
GND
BO
GATE
OVP
ISL6731A
FB
COMP
SKIP VREG
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. PFC EFFICIENCY
FN8582 Rev 1.00
February 13, 2015
Page 1 of 20
ISL6731A, ISL6731B
Pin Configuration
ISL6731A, ISL6731B
(14 LD SOIC)
TOP VIEW
NC 1
GND 2
ISEN 3
ICOMP 4
VIN 5
BO 6
OVP 7
14 GATE
13 NC
12 VCC
11 VREG
10 SKIP
9 FB
8 COMP
Pin Descriptions
PIN #
1, 13
2
3
4
5
I/O
-
-
I
I/O
I
SYMBOL
NC
GND
ISEN
ICOMP
VIN
Not Connected. Must be floating.
Ground pin. All voltage levels refer to this pin.
Current sense pin. The current through this pin is proportional to the inductor current.
Current error amplifier output pin.
Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider
from the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the
input current. The phase lag is required to compensate the phase lead generated by the EMI filter.
This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will
follow the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor R
IS
. The decoupling capacitor
provides ripple filtering. When the voltage at the BO pin (V
BO
) drops below brownout voltage threshold, the controller
enters shutdown mode and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling
threshold.
Overvoltage protection pin. Connect this pin to a resistor divider from the output. The resistor divider sets the OVP set point.
When the OVP pin voltage exceeds 104.5% of the reference voltage V
REF
, OVP is triggered and the gate drive is disabled.
Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will
slowly ramp up the voltage of the COMP pin.
Voltage feedback pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage.
When the FB pin voltage exceeds 104% of V
REF
, OVP is triggered and gate drive is disabled. When the FB pin drops below
10% of V
REF
, the device is put into shutdown mode. There is an internal pull-down current source for open loop protection.
This pin has dual functions. Connecting this pin to ground disables the light load skip function. An internal 20μA current
sources out of this pin. Connect a resistor from this pin to the ground to set the average power trip point. The converter
exits the skip mode when either the VFB drops below 88% of V
REF
, or the ISEN current goes above 29μA.
Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND
with a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.
Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.
Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and
1.5A source capability.
DESCRIPTION
6
I/O
BO
7
8
9
I
I/O
I
OVP
COMP
FB
10
I/O
SKIP
11
12
14
-
I
O
VREG
VCC
GATE
FN8582 Rev 1.00
February 13, 2015
Page 2 of 20
ISL6731A, ISL6731B
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL6731AFBZ
ISL6731BFBZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL6731A, ISL6731B.
For more information on MSL please see techbrief
TB363.
PART
MARKING
ISL 6731AFBZ
ISL 6731BFBZ
TEMP.
RANGE (°C)
-40 to +125
-40 to +125
14 Ld SOIC
14 Ld SOIC
PACKAGE
(Pb-Free)
PKG.
DWG. #
M14.15
M14.15
TABLE 1. KEY DIFFERENCES IN FAMILY OF ISL6731
VERSION
Switching Frequency
ISL6731A
124kHz
ISL6731B
62kHz
FN8582 Rev 1.00
February 13, 2015
Page 3 of 20
Block Diagram
EMI CHOKE
FN8582 Rev 1.00
February 13, 2015
Page 4 of 20
ISL6731A, ISL6731B
V
I
L
F
L
C
F1
Q
1
D
V
OUT
C
OUT
V
LINE
C
F3
L
m
C
F2
D
F1
D
F2
R
CS
C
REG
VCC
VREG
CURRENT
MIRROR
2:1
R
SEN
ISEN
I OC
I CS > -------------
-
2
I CS
OTP
UVLO
LINEAR
REGULATOR
VCC
GATE
CONTROL
LOGIC
GND
PWM
COMP
CEQ GEN.
ICOMP
I
REF
Gmi
0.25 ¥ VIN
----------------------------COMPB
2
BO
R
IN2
VIN
COMPB
COMP-1V
V
R ¥I
IS ISEN
= ---------------------------------
-
CS
2
OSCILLATOR
SKIP
Vro2
R
OV1
OVP
Vro1
R
OV2
R
IS
SOFT-START
ENABLE
Vref
R
FB2
SKIP
CLAMP
OVERPOWER
LIMIT
Gmv
FB
R
FB1
R
IN1
20µA
I
FB
BO
C
BO
SKIP
COMP
Application Schematics
Typical 300W Application Schematic
D1
IN5406
L1
0u
L2
1.5m
D2
2
1
VOUT
DC+
TP9
P2
1
C19
C1
0.1
270u
450V
P1
AC1
2
3
2
3
F1 8A
+
TP12
GATE1
C22
-
DB1
GBU806
C3
680n
R28 0.22
R27 0.22
R5 0.22
C8
220n
D8 D7
S1M S1M
R14
30k
47n
C20
R2
2.2
2
P4
AC2
L4
2.2m
L3
2.2m
R3
2M
1
4
1
4
R4
51k
3
470n
RV1
MOV /DNP
2
11
12
1
13
6
10
8
3
2
FN8582 Rev 1.00
February 13, 2015
Page 5 of 20
ISL6731A, ISL6731B
C3D04060A
SPP20N60C3
Q1
1
C21
0.1
R1
2M
390V
UNIVERSAL INPUT
90~265Vac
C2
470n
P3
GND
2.2n
C35
2.2n
C36
2.2n 2.2n
C5 C6
DZ1
3.3V
PE
P5
C12
DNP
C9
TP7
DNP
1u
DNP
VCC
VREG
GATE
C11
TP8
R8
R24
1n
C7
470k
U1
3.3M
6.8n
1u
VREG Lin.Reg. VCC
C10
GATE
14
UVLO LOGIC
4
ICOMP
R9
TP6
R11
3k
GND
2
ICOMP
CEQ OTP
470k
3
ISENI MIRROR
Gen
2:1
TP5
ISEN
OVP
7
PWM
Vin*C
I*= 4*BO*BO
I*
gm
VIN
C23
2.5V
5
VIN
1n
C SKIP OPL
TP3
FB
9
gm
+
-
SKIP
COMP
BO
R13
C13
VCC
ISL6731A/B
5.76k
47p
R21
TP4 69.8K
TP2
25k
R22
DNP
2N7002
BO
COMP
Q2
1
DNP
DNP
P8
C15
R18
150n
C14
62k
DNP
C17
470n
R20
1n
10k
DNP
C18
P9
1u
DNP
R23
3.3M
3.3M
R6
TP10
C26
2.2n
R10
3.3M
DNP
TP11
OVP
42.2k
R25
R26
49.9
TP1
R17
0
C16
100n
R19
42.2k
FB
VCC
GND
P6
P7