Operating Temperature Range ......................... -40°C to +125°C
Storage Temperature Range ............................ -65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
µDFN
Junction-to-Ambient Thermal Resistance (θ
JA
).........477°C/W
Junction-to-Case Thermal Resistance (θ
JC
)................122C/W
Thin SOT23
Junction-to-Ambient Thermal Resistance (θ
JA
)..........110°C/W
Junction-to-Case Thermal Resistance (θ
JC
).................50°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four layer
board. For detailed information on package thermal considerations refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
CC
= 1.5V to 5.5V, T
A
= -40°C to +125°C, unless otherwise specified. Typical values are at V
CC
= 3.3V and T
A
= +25°C, unless
otherwise noted.) (Note 2)
PARAMETER
SUPPLY
Operating Voltage Range
Undervoltage Lockout (Note 3)
V
CC
Supply Current
IN
Threshold Voltage
Hysteresis
Input Current (Note 4)
CDELAY
Delay Charge Current
Delay Threshold
CDELAY Pulldown Resistance
ENABLE/ENABLE
Input Low Voltage
Input High Voltage
Input Leakage Current
V
IL
V
IH
I
LEAK
ENABLE,
ENABLE
= V
CC
or GND
1.4
-100
+100
0.4
V
V
nA
I
CD
V
TCD
R
CDELAY
CDELAY rising
200
0.95
250
1.00
130
300
1.05
500
nA
V
Ω
V
TH
V
HYST
I
IN
V
IN
rising, 1.5V < V
CC
< 5.5V
V
IN
falling
V
IN
= 0V or V
CC
-15
0.491
0.5
5
+15
0.509
V
mV
nA
V
CC
UVLO
I
CC
V
CC
falling
V
CC
= 3.3V, no load
1.5
1.20
10
5.5
1.35
20
V
V
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
www.maximintegrated.com
Maxim Integrated │ 2
MAX6895–MAX6899
Ultra-Small, Adjustable Sequencing/
Supervisory Circuits
Electrical Characteristics (continued)
(V
CC
= 1.5V to 5.5V, T
A
= -40°C to +125°C, unless otherwise specified. Typical values are at V
CC
= 3.3V and T
A
= +25°C, unless
otherwise noted.) (Note 2)
PARAMETER
OUT/OUT
Output Low Voltage (Open-Drain
or Push-Pull)
V
CC
≥ 1.2V, I
SINK
= 90µA,
MAX6895/MAX6897/MAX6899 only
V
CC
≥ 2.25V, I
SINK
= 0.5mA
V
CC
≥ 4.5V, I
SINK
= 1mA
Output High Voltage (Push-Pull)
V
OH
V
CC
≥ 2.25V, I
SOURCE
= 500µA
V
CC
≥ 4.5V, I
SOURCE
= 800µA
Output high impedance, V
OUT
= 28V
0.8 x
V
CC
0.8 x
V
CC
1
0.3
0.3
0.4
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
OL
V
Output Open-Drain Leakage
Current
TIMING
IN to OUT/OUT Propagation
Delay
Startup Delay (Note 5)
ENABLE/ENABLE Minimum
Input Pulse Width
ENABLE/ENABLE Glitch
Rejection
ENABLE/ENABLE to OUT/OUT
Delay
I
LKG
µA
t
DELAY
t
DL
V
IN
rising
V
IN
falling
C
CDELAY
= 0µF
C
CDELAY
= 0.047µF
40
190
16
2
µs
ms
µs
ms
µs
t
PW
1
100
ns
ns
ns
µs
ms
t
OFF
t
PROPP
From device enabled to device disabled
From device disabled to device enabled
(P version)
From device disabled
to device enabled
(A version)
C
CDELAY
= 0µF
C
CDELAY
= 0.047µF
150
150
20
190
ENABLE/ENABLE to OUT/OUT
Delay
t
PROPA
Note 2:
All devices are production tested at T
A
= +25°C. Limits over temperature are guaranteed by design.
Note 3:
When V
CC
falls below the UVLO threshold, the outputs will deassert (OUT goes low,
OUT
goes high). When V
CC
falls
below 1.2V, the out cannot be determined.
Note 4:
Guaranteed by design.
Note 5:
During the initial power-up, V
CC
must exceed 1.5V for at least 2ms before the output is guaranteed to be in the correct
state.
www.maximintegrated.com
Maxim Integrated │ 3
MAX6895–MAX6899
Ultra-Small, Adjustable Sequencing/
Supervisory Circuits
Typical Operating Characteristics
(V
CC
= 3.3V and T
A
= +25°C, unless otherwise noted.)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6895 toc01
MAX6895 toc02
18
16
14
I
CC
(µA)
10
8
6
4
2
0
V
CC
= 1.5V
V
CC
= 3V
12
V
CC
= 5V
0.5008
0.5006
0.5004
V
TH
(V)
0.5002
0.5000
0.4998
0.4996
0.4994
0.4992
0.4990
I
CC
(µA)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
CC
(V)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (C)
MAX6895 toc04
MAX6895 toc05
4500
4000
3500
t
DELAY
(ms)
3000
2500
2000
1500
1000
500
0
V
CC
= 1.5V
1.2
V
CC
= 3V
V
OL
(V)
0.9
0.6
0.3
0
V
CC
= 5V
4.5
4.0
3.5
V
OH
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
V
CC
= 1.5V
V
CC
= 3V
0 100 200 300 400 500 600 700 800 900 1000
C
CDELAY
(nF)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
SINK
(mA)
0
2
4
6
8
10 12 14 16 18 20
I
SOURCE
(mA)
MAXIMUM TRANSIENT DURATION (µs)
500
400
300
200
100
0
RESET
OCCURS
MAX6895 toc07
600
MAXIMUM TRANSIENT DURATION
vs. INPUT OVERDRIVE
ENABLE TURN-ON/OFF
(MAX6896P)
MAX6895 toc08
ENABLE TURN-ON/OFF DELAY
(MAX6895A)
MAX6895 toc09
V
OUT
2V/div
OUT
2V/div
V
ENABLE
2V/div
0
10 20 30 40 50 60 70 80 90 100
V
OVERDRIVE
(mV)
100ns/div
40µs/div
ENABLE
2V/div
www.maximintegrated.com
Maxim Integrated │ 4
MAX6895 toc06
5000
OUT DELAY
vs. C
CDELAY
OUTPUT LOW VOLTAGE
vs. SINK CURRENT
1.5
5.0
OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT
V
CC
= 5V
MAX6895 toc03
20
SUPPLY CURRENT
vs. TEMPERATURE
0.5010
IN THRESHOLD
vs. TEMPERATURE
MAX6895–MAX6899
Ultra-Small, Adjustable Sequencing/
Supervisory Circuits
Pin Description
PIN
MAX6895/
MAX6897
µDFN
THIN
SOT23
MAX6896/
MAX6898
µDFN
THIN
SOT23
MAX6899
µDFN
THIN
SOT23
Active-High Logic-Enable Input. Drive ENABLE low to
immediately deassert the output to its false state (OUT =
low or
OUT
= high) independent of V
IN
. With V
IN
above
V
TH
, drive ENABLE high to assert the output to its true
state (OUT = high or
OUT
= low) after the adjustable
delay period (MAX689_A) or a 150ns propagation delay
(MAX689_P).
Active-Low Logic-Enable Input. Drive
ENABLE
high to
immediately deassert the output to its false state (OUT =
low or
OUT
= high) independent of V
IN
. With V
IN
above
V
TH
, drive
ENABLE
low to assert the output to its true
state (OUT = high or
OUT
= low) after the adjustable
delay period (MAX689_A) or a 150ns propagation delay
(MAX689_P).
Ground
High-Impedance Monitor Input. Connect IN to an
external resistive divider to set the desired monitored
threshold. The output changes state when V
IN
rises
above 0.5V and when V
IN
falls below 0.495V.
Active-High Sequencer/Monitor Output, Push-Pull
(MAX6895/MAX6899) or Open-Drain (MAX6897). OUT
is asserted to its true state (OUT = high) when V
IN
is above V
TH
and the enable input is in its true state
(ENABLE = high or
ENABLE
= low) for the capacitor-
adjusted delay period. OUT is deasserted to its false
state (OUT = low) immediately after V
IN
drops below
V
TH
- 5mV or the enable input is in its false state
(ENABLE = low or
ENABLE
= high). The open-drain
version requires an external pullup resistor.
Active-Low Sequencer/Monitor Output, Push-Pull
(MAX6896) or Open-Drain (MAX6898). OUT is asserted
to its true state (OUT = low) when V
IN
is above V
TH
and the enable input is in its true state (ENABLE = high
or
ENABLE
= low) after the CDELAY adjusted timeout
period. OUT is deasserted to its false state (OUT =
high) immediately after V
IN
drops below V
TH
- 5mV or
the enable input is in its false state (ENABLE = low or
ENABLE
= high). The open-drain version requires an
external pullup resistor.
Capacitor-Adjustable Delay. Connect an external
capacitor (C
CDELAY
) from CDELAY to GND to set the
IN to OUT (and ENABLE to OUT or
ENABLE
to OUT
for A version devices) delay period. t
DELAY
= (C
CDELAY
x 4.0 x 10
6
) + 40µs. There is a fixed short delay (40µs,
typ) for the output deasserting when V IN falls below
VTH.
Supply Voltage Input. Connect a 1.5V to 5.5V supply
FPGA/CPLD
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