EL7640, EL7641, EL7642
S
R NEW DESIGN
OMMENDED FO
NO T REC
EMENT PART
ENDED REPL AC
R E C OM M
ISL97645A
DATASHEET
FN7415
Rev 2.00
February 22, 2006
TFT-LCD DC/DC with Integrated Amplifiers
The EL7640, EL7641, and EL7642 integrate a high
performance boost regulator with 2 LDO controllers for V
ON
and V
OFF
, a V
ON
-slice circuit with adjustable delay and
either one (EL7640), three (EL7641), or five amplifiers
(EL7642) for V
COM
and V
GAMMA
applications.
The boost converter in the EL7640, EL7641, and EL7642 is
a current mode PWM type integrating an 18V N-channel
MOSFET. Operating at 1.2MHz, this boost can operate in
either P-mode for superior transient response, or in PI-mode
for tighter output regulation.
Using external low-cost transistors, the LDO controllers
provide tight regulation for V
ON
, V
OFF
, as well as providing
start-up sequence control and fault protection.
The amplifiers are ideal for V
COM
and V
GAMMA
applications, with 150mA peak output current drive, 12MHz
bandwidth, and 12V/s slew rate. All inputs and outputs are
rail-to-rail.
Available in the 32 Ld thin QFN (5mm x 5mm) Pb-free
packages, the EL7640, EL7641, and EL7642 are specified
for operation over the -40°C to +85°C temperature range.
Features
• Current mode boost regulator
- Fast transient response
- 1% accurate output voltage
- 18V/3A integrated FET
- >90% efficiency
• 2.6V to 5.5V V
IN
supply
• 2 LDO controllers for V
ON
and V
OFF
- 2% output regulation
- V
ON
-slice circuit
• High speed amplifiers
- 150mA short-circuit output current
- 12V/s slew rate
- 12MHz -3dB bandwidth
- Rail-to-rail inputs and outputs
• Built-in power sequencing
• Internal soft-start
• Multiple overload protection
• Thermal shutdown
Ordering Information
PART NUMBER
(Note)
EL7640ILTZ
EL7640ILTZ-T7
EL7640ILTZ-T13
EL7641ILTZ
EL7641ILTZ-T7
EL7641ILTZ-T13
EL7642ILTZ
EL7642ILTZ-T7
EL7642ILTZ-T13
PART
TAPE & PACKAGE
MARKING REEL
(Pb-Free)
7640ILTZ
7640ILTZ
7640ILTZ
7641ILTZ
7641ILTZ
7641ILTZ
7642ILTZ
7642ILTZ
7642ILTZ
-
7”
13”
-
7”
13”
-
7”
13”
32 Ld 5x5
Thin QFN
32 Ld 5x5
Thin QFN
32 Ld 5x5
Thin QFN
32 Ld 5x5
Thin QFN
32 Ld 5x5
Thin QFN
32 Ld 5x5
Thin QFN
32 Ld 5x5
Thin QFN
32 Ld 5x5
Thin QFN
32 Ld 5x5
Thin QFN
PKG.
DWG. #
MDP0051
• 32 Ld 5x5 thin QFN package
• Pb-Free plus anneal available (RoHS compliant)
Applications
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
• TFT-LCD panels
• LCD monitors
• Notebooks
• LCD-TVs
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
FN7415 Rev 2.00
February 22, 2006
Page 1 of 19
EL7640, EL7641, EL7642
Pinouts
EL7640
(32 LD QFN)
TOP VIEW
28 DRVN
26 DRVP
32 COM
32 COM
31 DRN
31 DRN
EL7641
(32 LD QFN)
TOP VIEW
28 DRVN
26 DRVP
27 FBN
27 FBN
25 FBP
SRC 1
REF 2
AGND 3
PGND 4
OUT1 5
NEG1 6
POS1 7
NC 8
IC 10
BGND 11
NC 12
NC 13
SUP 14
NC 15
NC 16
NC 9
THERMAL
PAD
24 COMP
23 FB
22 IN
21 LX
20 NC
19 NC
18 IC
17 NC
SRC 1
REF 2
AGND 3
PGND 4
OUT1 5
NEG1 6
POS1 7
OUT2 8
POS2 10
BGND 11
NC 12
NC 13
SUP 14
POS3 15
NEG3 16
NEG2 9
THERMAL
PAD
25 FBP
24 COMP
23 FB
22 IN
21 LX
20 NC
19 NC
18 IC
17 OUT3
29 DEL
NC = NOT INTERNALLY CONNECTED
IC = INTERNALLY CONNECTED
NC = NOT INTERNALLY CONNECTED
IC = INTERNALLY CONNECTED
EL7642
(32 LD QFN)
TOP VIEW
28 DRVN
26 DRVP
32 COM
31 DRN
27 FBN
SRC 1
REF 2
AGND 3
PGND 4
OUT1 5
NEG1 6
POS1 7
OUT2 8
POS2 10
BGND 11
POS3 12
OUT3 13
SUP 14
POS4 15
NEG4 16
NEG2 9
THERMAL
PAD
25 FBP
29 DEL
30 CTL
24 COMP
23 FB
22 IN
21 LX
20 OUT5
19 NEG5
18 POS5
17 OUT4
FN7415 Rev 2.00
February 22, 2006
29 DEL
30 CTL
30 CTL
Page 2 of 19
EL7640, EL7641, EL7642
Absolute Maximum Ratings
(T
A
= 25°C)
IN, CTL to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
COMP, FB, FBP, FBN, DEL, REF to AGND. . . . . -0.3V to V
IN
+0.3V
PGND, BGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
SUP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V
DRVP, SRC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V
POS1, NEG1, OUT1, POS2, NEG2, OUT2, POS3, OUT3,
POS4, NEG4, OUT4, POS5, OUT5 to AGND . . -0.3V to V
SUP
+0.3V
DRVN to AGND . . . . . . . . . . . . . . . . . . . . . . . V
IN
-20V to V
IN
+0.3V
COM, DRN to AGND . . . . . . . . . . . . . . . . . . . . -0.3V to V
SRC
+0.3V
LX Maximum Continuous RMS Output Current. . . . . . . . . . . . . 1.6A
OUT1, OUT2, OUT3, OUT4, OUT5
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±75mA
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Continuous Junction Temperature . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
SUPPLY
V
IN
V
LOR
V
LOF
I
S
I
SS
T
FD
V
REF
V
IN
= 3V, V
BOOST
= V
SUP
= 12V, V
SRC
= 20V, Over temperature from -40°C to 85°C.
Unless Otherwise Specified.
CONDITIONS
MIN
TYP
MAX
UNIT
DESCRIPTION
Input Supply Range
Undervoltage Lockout Threshold
Undervoltage Lockout Threshold
Quiescent Current
Quiescent Current - Switching
Fault Delay Time
Reference Voltage
V
IN
rising
V
IN
falling
LX not switching
LX switching
C
DEL
= 220nF
T
A
= 25°C
2.6
2.4
2.2
2.5
2.3
5.5
2.6
2.4
2.5
5
52
10
V
V
V
mA
mA
ms
1.19
1.187
1.215
1.215
140
1.235
1.238
V
V
°C
SHUTDN
Thermal Shutdown Temperature
MAIN BOOST REGULATOR
V
BOOST
F
OSC
D
CM
V
FBB
Output Voltage Range
Oscillator Frequency
Maximum Duty Cycle
Boost Feedback Voltage
T
A
= 25°C
(Note 1)
V
IN
+
15%
1050
82
1.192
1.188
V
FTB
V
BOOST
/
I
BOOST
V
BOOST
/
V
IN
I
FB
gmV
R
ON
LX
I
LEAK
LX
I
LIM
LX
t
SS
B
FB Fault Trip Level
Load Regulation
Line Regulation
Input Bias Current
FB Transconductance
LX On Resistance
LX Leakage Current
LX Current Limit
Soft-Start Period
V
FB
= 1.35V, V
LX
= 13V
Duty cycle = 65% (Note 1)
C
DEL
= 220nF
Falling edge
50mA < I
LOAD
< 250mA
V
IN
= 2.6V to 5.5V
V
FB
= 1.35V
dI = ±2.5µA at COMP, FB = COMP
160
160
0.02
3.0
2
40
0.85
1200
85
1.205
1.205
0.925
0.1
0.08
500
1.218
1.222
1.020
18
1350
V
kHz
%
V
V
V
%
%/V
nA
µA/V
m
µA
A
ms
FN7415 Rev 2.00
February 22, 2006
Page 3 of 19
EL7640, EL7641, EL7642
Electrical Specifications
PARAMETER
V
IN
= 3V, V
BOOST
= V
SUP
= 12V, V
SRC
= 20V, Over temperature from -40°C to 85°C.
Unless Otherwise Specified.
(Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
OPERATIONAL AMPLIFIERS
V
SUP
I
SUP
V
OS
I
B
CMIR
CMRR
A
OL
V
OH
Supply Operating Range
Supply Current per Amplifier
Offset Voltage
Input Bias Current
Common Mode Input Range
Common Mode Rejection Ratio
Open Loop Gain
Output Voltage High
I
OUT
= 100µA
I
OUT
= 5mA
V
OL
Output Voltage Low
I
OUT
= -100µA
I
OUT
= -5mA
I
SC
I
CONT
PSRR
BW
-3dB
GBWP
SR
POSITIVE LDO
V
FBP
Positive Feedback Voltage
I
DRVP
= 100µA, T
A
= 25°C
I
DRVP
= 100µA
V
FTP
I
BP
V
POS
/
I
POS
I
DRVP
I
LEAK
P
t
SS
P
NEGATIVE LDO
V
FBN
FBN Regulation Voltage
I
DRVN
= 0.2mA, T
A
= 25°C
I
DRVN
= 0.2mA
V
FTN
I
BN
V
FBN
Fault Trip Level
Negative LDO Input Bias Current
FBN Load Regulation
I
DRVN
I
LEAK
N
t
SS
N
Source Current
DRVN Off Leakage Current
Soft-start Period
V
FBN
rising
V
FBN
= 250mV
V
DRVN
= -6V, I
DRVN
= 2µA to 20µA
V
FBN
= 500mV, V
DRVN
= -6V
V
FBP
= 1.35V, V
DRVP
= 30V
C
DEL
= 220nF
2
0.173
0.171
380
-50
0.5
4
0.1
2
10
0.203
0.203
430
0.233
0.235
480
50
V
V
mV
nA
%
mA
µA
ms
V
FBP
Fault Trip Level
Positive LDO Input Bias Current
FBP Load Regulation
Sink Current
DRVP Off Leakage Current
Soft-Start Period
V
FBP
falling
V
FBP
= 1.4V
V
DRVP
= 25V, I
DRVP
= 0 to 20µA
V
FBP
= 1.1V, V
DRVP
= 10V
V
FBP
= 1.4V, V
DRVP
= 30V
C
DEL
= 220nF
2
1.176
1.176
0.82
-50
0.5
4
0.1
2
10
1.2
1.2
0.9
1.224
1.229
0.98
50
V
V
V
nA
%
mA
µA
ms
Short-Circuit Current
Continuous Output Current
Power Supply Rejection Ratio
-3dB Bandwidth
Gain Bandwidth Product
Slew Rate
100
±50
60
100
12
8
12
V
SUP
-15
V
SUP
-250
-50
0
60
90
110
V
SUP
-2
V
SUP
-150
2
100
150
30
150
4.5
600
3
18
800
12
+50
V
SUP
V
µA
mV
nA
V
dB
dB
mV
mV
mV
mV
mA
mA
dB
MHz
MHz
V/µs
FN7415 Rev 2.00
February 22, 2006
Page 4 of 19
EL7640, EL7641, EL7642
Electrical Specifications
PARAMETER
V
ON
-SLICE CIRCUIT
V
LO
V
HI
I
LEAK
CTL
t
D
rise
CTL Input Low Voltage
CTL Input High Voltage
CTL Input Leakage Current
CTL to OUT Rising Prop Delay
V
IN
= 2.6V to 5.5V
V
IN
= 2.6V to 5.5V
CTL = AGND or IN
1k from DRN to 8V, V
CTL
= 0V to 3V step,
no load on OUT, measured from V
CTL
= 1.5V
to OUT = 20%
1k from DRN to 8V, V
CTL
= 3V to 0V step,
no load on OUT, measured from V
CTL
= 1.5V
to OUT = 80%
0.6V
IN
-1
100
1
0.4V
IN
V
V
µA
ns
V
IN
= 3V, V
BOOST
= V
SUP
= 12V, V
SRC
= 20V, Over temperature from -40°C to 85°C.
Unless Otherwise Specified.
(Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
t
D
fall
CTL to OUT Falling Prop Delay
100
ns
V
SRC
ISRC
SRC Input Voltage Range
SRC Input Current
Start-up sequence not completed
Start-up sequence completed
150
150
5
30
350
1000
30
250
250
10
60
1800
V
µA
µA
R
ON
SRC
R
ON
DRN
R
ON
COM
SEQUENCING
t
ON
t
DEL1
t
DEL2
t
DEL3
C
DEL
NOTE:
SRC On Resistance
DRN On Resistance
COM to GND On Resistance
Start-up sequence completed
Start-up sequence completed
Start-up sequence not completed
Turn On Delay
Delay Between V
BOOST
and V
OFF
Delay Between V
ON
and V
OFF
Delay From V
ON
to V
ON
-slice Enabled
Delay Capacitor
C
DLY
= 0.22µF (See Figure 23)
C
DLY
= 0.22µF (See Figure 23)
C
DLY
= 0.22µF (See Figure 23)
C
DLY
= 0.22µF (See Figure 23)
50
30
10
17
10
220
ms
ms
ms
ms
nF
1. Guaranteed by design.
FN7415 Rev 2.00
February 22, 2006
Page 5 of 19
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