TB62802AFG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62802AFG
CCD Clock Drivers
The TB62802AFG is a clock distribution driver for CCD linear
image sensors.
The IC can functionally drive the CCD input capacitance. It
also supports inverted outputs, eliminating the need for cross
point control.
The IC contains a 1-to-4 clock distribution driver and 4-bit
buffer.
The suffix (G) appended to the part number represents a Lead
(Pb) -Free product.
Features
•
High drivability:
In the case of 4-bit distribution driver ,
Guaranteed driving 250 pF load capacitance @fclock = 25 MHz.
In the case of 2-bit distribution driver
(φ
only or
φ
only),
Guaranteed driving 250 pF load capacitance @fclock = 35 MHz.
•
Operating temperature range: Ta = 0°C to 60°C
Weight: 0.5 g (typ.)
Pin Connection
(top view)
OUT_cont
2B_in
CP_in
V
CC1
1
2
3
4
16
15
14
13
2B_out
CP_out
φ
φ
GND1
GND2
V
CC2
CK_in
SH_in
RS_in
5
6
7
8
12
11
10
9
φ
φ
SH_out
RS_out
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2011-07-15
TB62802AFG
Logic Diagram
φ
φ
CK_in
φ
φ
CP_in
SH_in
RS_in
2B_in
OUT_cont
CP_out
SH_out
RS_out
2B_out
Pin Description
Pin No.
1
2
3
4
⎯
5
6
7
8
9
10
11
12
⎯
13
14
15
16
Pin Name
OUT_cont
2B_in
CP_in
V
CC1
GND1
V
CC2
CK_in
SH_in
RS_in
RS_out
SH_out
φ
φ
Functions
Output control pin
Light load drive input
Light load drive input
Light load power supply
Light load ground
Heavy load power supply
Heavy load drive input
Light load drive input
Light load drive input
Light load drive output (not inverted)
Light load drive output (not inverted)
Heavy load drive output (not inverted)
Heavy load drive output (inverted)
Heavy load ground
Heavy load drive output (inverted)
Heavy load drive output (not inverted)
Light load drive output (not inverted)
Light load drive output (not inverted)
Remarks
Internal pull down R=250 k ohm
Driver input for CCD last-stage clock
CCD clamp gate driver input
⎯
⎯
⎯
Driver input for CCD transfer clock
CCD shift gate driver input
CCD reset gate driver input
CCD reset gate driver output
CCD shift gate driver output
Driver output for CCD transfer clock
Driver output for CCD transfer clock
⎯
Driver output for CCD transfer clock
Driver output for CCD transfer clock
CCD clamp gate driver output
Driver output for CCD last-stage clock
GND2
φ
φ
CP_out
2B_out
Note1: The internal circuits for heavy load drive pins
φ
and
φ
have the same configuration as those of light load
drive pins RS_out, SH_out, CP_out and 2B_out. Thus, these internal circuits have the same characteristics.
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TB62802AFG
Truth Table
Input
Pin Name
Logic
Pin Name
Logic
L
CK_in
H
L
H
L
H
L
H
L
H
Pin Name
Output
Logic
L
H
H
L
L
H
L
H
L
H
L
H
L
φ
φ
φ
φ
CP_in
OUT_cont
L
SH_in
CP_out
SH_out
RS_in
RS_out
2B_in
H
2B_out
All Output
⎯
⎯
Absolute Maximum Ratings
(Ta
=
25°C)
Characteristic
Power supply voltage
Input voltage
Output voltage
Output current
High level
excluding other
Low level
than
φ
,
φ
outputs
Symbol
V
CC
V
IN
V
O
I
OH
(O)
I
OL
(O)
I
OH
(
φ
)
I
OL
(
φ
)
T
stg
T
j
Rating
Unit
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
−
0.3 to 6.0
−
0.3 to
V
CC
+
0.3
−
0.5 to V
CC
−
16.0
+
16.0
−
150
150
φ
output current
Storage temperature
High level
Low level
−
40 to 150
150
83
Junction temperature
Thermal resistance Chip to ambient air
θ
ja
Note2: Output current is specified as follows: V
OH
=
4.0 V, V
OL
=
0.5 V.
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TB62802AFG
Operating Conditions
(Ta
=
25°C)
Characteristic
Power supply voltage
Input voltage
Output voltage
Output current
excluding
φ
,
φ
outputs
High level
Low level
High level
Low level
Symbol
V
CC
V
IN
V
O
I
OH
(O)
I
OL
(O)
I
OH
(
φ
)
I
OL
(
φ
)
Min
4.7
0
0
Typ.
5.0
Max
5.5
V
CC
V
CC
Unit
V
V
V
mA
mA
mA
mA
°C/W
°C
ns
⎯
⎯
⎯
⎯
⎯
⎯
12
25
2.5
⎯
⎯
⎯
⎯
⎯
0
−
8.0
8.0
φ
output current
Thermal resistance
(chip to case)
Operating temperature
Input rise/fall time
−
10.0
10.0
θ
jc
T
opr
(Note3)
tri/tfi
⎯
60
5.0
⎯
Note3: There is no hysteresis in the input block of this IC. Therefore attention should be given to the following:
A CMOS integrated circuit charges and discharges the capacitance load (internal equivalent capacitance) of
the internal circuit while operating. The charged or discharged current flows in the package of the IC and
inductance of transmission line, which causes inductive spike voltage to be generated.
When the spike voltage is generated in the reference GND, it affects the amplitude of an input signal. The
amplitude seems to be fluctuating compared to when no spike voltage is generated in the reference GND.
In this case, some induced spike waveforms exceed the input threshold level. For low-frequency inputs, the
rate at which a spike exceeds the level increases, resulting in unstable output.
Therefore, do not apply input signals lower than 1
μs.
When designing a board, be sure to take transmission
line inductance into consideration.
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TB62802AFG
Electrical Characteristics
DC Characteristics
(unless otherwise specified, V
CC
=
4.7 to 5.5 V, Ta
=
0 to 60°C)
Characteristic
Input voltage
High
Low
Symbol
V
IH
V
IL
V
OH
(O)
V
OL
(O)
Test
Circuit
1
I
OH
= −
50
μ
A
I
OH
= −
8 mA
I
OL
=
50
μ
A
I
OL
=
8 mA
I
OH
= −
10 mA
V
OH
(
φ
/
φ
)
2,3
I
OH
= −
30 mA
I
OH
= −
120 mA
I
OL
=
50
μ
A
V
OL
(
φ
/
φ
)
4,5
I
OL
=
30 mA
I
OL
=
120 mA
Input voltage
I
IN1
I
IN2
V
IN
(2,3,6,7,8pin)
6
Test Condition
V
CC
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
5.5
5.5
Min
2.0
0
4.5
3.9
0
0
4.5
3.9
3.0
0
0
0
Typ.
Max
V
CC
0.8
V
CC
V
CC
0.2
0.7
V
CC
V
CC
V
CC
0.3
0.5
2.0
1.0
35
V
V
Unit
V
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2
Output voltage excluding
φ
,
φ
outputs
4
φ
output voltage
=
V
CC
or GND
V
IN(1pin)
=
V
CC
or GND
For light load output, all bits
are High.
For heavy load output, 2 bits
are High.
2 bits are Low.
Out_cont
=
“H”
One input
: V
IN
=
0.5 V or V
CC
−
2.1 V
Other inputs
: V
IN
=
V
CC
or GND
−
1.0
⎯
μ
A
Total
Static current
consumption
I
CC
7
5.5
⎯
⎯
15.0
Forced low
for all bits
Each bit
I
CCL
⎯
5.5
⎯
⎯
30.0
mA
Δ
I
CC
8
⎯
⎯
⎯
1.5
Output off mode supply
voltage
V
POR
(Note Light load power supply
4) (V
CC1
) reference
⎯
⎯
3.0
⎯
V
Note4: Refer to the description of the P.O.R below.
Mode in Which Output Is Held at Low at Power-On
(P.O.R: Power On Reset circuit)
To eliminate the unstable period for the internal logic, this IC incorporates a function for monitoring the light
load power supply (V
CC1
) at power-on to maintain the outputs at Low.
•
At power-on, all output are held at Low until light load power supply (V
CC1
) reaches the voltage level of 3 V.
•
•
When the light load power supply (V
CC1
) voltage is higher than 3 V (typ.), the internal logic operates according
to input signals.
For normal operation, be sure to use a power supply of 4.7 V or higher as guaranteed.
Supply voltage
Power
V
CC
3V
Output signal waveform
V
CC
Pulse
generator
DUT
Output signal waveform
P.O.R test circuit
GND
Low level state
Time
Refer to Subsection 10.
“Propagation Delay Time” in AC Parameters.
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2011-07-15
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