Intel® Atom™ Processor N400 &
N500 Series
Datasheet– Volume 2
This is volume 2 of 2. Refer to Document Ref# 322847 for Volume 1
June 2011
Document Number: 322848-003
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2
Datasheet
Contents
8
Processor Configuration Registers
........................................................................... 10
8.1
8.2
Register Terminology ......................................................................................... 10
System Address Map.......................................................................................... 12
8.2.1 Legacy Address Range ............................................................................ 14
8.2.2 Main Memory Address Range (1 MB to TOLUD)........................................... 18
8.2.3 PCI Memory Address Range (TOLUD – 4 GB).............................................. 20
8.2.4 Graphics Memory Address Ranges ............................................................ 22
8.2.5 System Management Mode (SMM) ............................................................ 25
8.2.6 Memory Shadowing ................................................................................ 28
8.2.7 I/O Address Space.................................................................................. 28
8.2.8 Memory Controller Decode Rules and Cross-Bridge Address Mapping ............. 29
Processor Register Introduction .......................................................................... 29
I/O Mapped Registers ........................................................................................ 30
PCI Device 0 ..................................................................................................... 30
8.5.1 VID - Vendor Identification ...................................................................... 32
8.5.2 DID - Device Identification....................................................................... 33
8.5.3 PCICMD - PCI Command ......................................................................... 34
8.5.4 PCISTS - PCI Status ............................................................................... 36
8.5.5 RID - Revision Identification .................................................................... 38
8.5.6 CC - Class Code ..................................................................................... 38
8.5.7 MLT - Master Latency Timer ..................................................................... 39
8.5.8 HDR - Header Type................................................................................. 40
8.5.9 SVID - Subsystem Vendor Identification .................................................... 40
8.5.10 SID - Subsystem Identification ................................................................. 41
8.5.11 CAPPTR - Capabilities Pointer ................................................................... 41
8.5.12 PXPEPBAR - PCI Express Egress Port Base Address ..................................... 42
8.5.13 MCHBAR - Processor Memory Mapped Register Range Base.......................... 43
8.5.14 GGC - Processor Graphics Control Register................................................. 44
8.5.15 DEVEN - Device Enable ........................................................................... 45
8.5.16 PCIEXBAR - PCI Express Register Range Base Address ................................ 46
8.5.17 DMIBAR - Root Complex Register Range Base Address ................................ 48
8.5.18 PAM0 - Programmable Attribute Map 0 ...................................................... 49
8.5.19 PAM1 - Programmable Attribute Map 1 ...................................................... 50
8.5.20 PAM2 - Programmable Attribute Map 2 ...................................................... 52
8.5.21 PAM3 - Programmable Attribute Map 3 ...................................................... 53
8.5.22 PAM4 - Programmable Attribute Map 4 ...................................................... 54
8.5.23 PAM5 - Programmable Attribute Map 5 ...................................................... 55
8.5.24 PAM6 - Programmable Attribute Map 6 ...................................................... 56
8.5.25 LAC - Legacy Access Control .................................................................... 57
8.5.26 REMAPBASE - Remap Base Address Register .............................................. 57
8.5.27 REMAPLIMIT - Remap Limit Address Register ............................................. 58
8.5.28 SMRAM - System Management RAM Control............................................... 58
8.5.29 ESMRAMC - Extended System Management RAM Control ............................. 60
8.5.30 TOM - Top of Memory ............................................................................. 61
8.5.31 TOUUD - Top of Upper Usable DRAM ......................................................... 62
8.5.32 GBSM - Graphics Base of Stolen Memory ................................................... 63
8.5.33 BGSM - Base of GTT Stolen Memory.......................................................... 63
8.5.34 TSEGMB - TSEG Memory Base.................................................................. 64
8.3
8.4
8.5
Datasheet
3
8.6
8.7
8.5.35 TOLUD - Top of Low Usable DRAM.............................................................65
8.5.36 ERRSTS - Error Status .............................................................................66
8.5.37 ERRCMD - Error Command.......................................................................68
8.5.38 SMICMD - SMI Command.........................................................................69
8.5.39 SKPD - Scratchpad Data ..........................................................................70
8.5.40 CAPID0 - Capability Identifier ...................................................................70
MCHBAR ...........................................................................................................74
8.6.1 CHDECMISC - Channel Decode Misc ..........................................................75
8.6.2 C0DRB0 – Channel 0 DRAM Rank Boundary Address 0 .................................76
8.6.3 C0DRB1 - Channel 0 DRAM Rank Boundary Address 1 .................................77
8.6.4 C0DRB2 - Channel 0 DRAM Rank Boundary Address 2 .................................77
8.6.5 C0DRB3 - Channel 0 DRAM Rank Boundary Address 3 .................................78
8.6.6 C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute ..........................................78
8.6.7 C0DRA23 - Channel 0 DRAM Rank 2,3 Attribute ..........................................79
8.6.8 C0CYCTRKPCHG - Channel 0 CYCTRK PCHG ...............................................80
8.6.9 C0CYCTRKACT - Channel 0 CYCTRK ACT ....................................................81
8.6.10 C0CYCTRKWR - Channel 0 CYCTRK WR......................................................82
8.6.11 C0CYCTRKRD - Channel 0 CYCTRK READ ...................................................83
8.6.12 C0CYCTRKREFR - Channel 0 CYCTRK REFR.................................................84
8.6.13 C0CKECTRL - Channel 0 CKE Control .........................................................84
8.6.14 C0REFRCTRL - Channel 0 DRAM Refresh Control .........................................86
8.6.15 C0ODTCTRL - Channel 0 ODT Control ........................................................88
8.6.16 C0GTEW - Channel 0 Memory Controller Throttling Event Weights. ................89
8.6.17 C0GTC - Channel 0 Memory Controller Throttling Control .............................90
8.6.18 C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event..........................91
8.6.19 C0DTAEW - Channel 0 DRAM Rank Throttling Active Event ...........................92
8.6.20 C0DTC - Channel 0 DRAM Throttling Control...............................................94
8.6.21 TSC1 - Thermal Sensor Control 1 ..............................................................95
8.6.22 TSS - Thermal Sensor Status ...................................................................97
8.6.23 TR - Thermometer Read ..........................................................................98
8.6.24 TSTTP - Thermal Sensor Temperature Trip Point .........................................99
8.6.25 DACGIOCTRL1 - DAC/GPIO Control Register 1 .......................................... 100
8.6.26 PMCFG - Power Management Configuration .............................................. 100
8.6.27 PMSTS - Power Management Status ........................................................ 102
DMIBAR ......................................................................................................... 103
8.7.1 DMIVCECH - DMI Virtual Channel Enhanced Capability ............................... 104
8.7.2 DMIPVCCAP1 - DMI Port VC Capability Register 1 ...................................... 105
8.7.3 DMIPVCCAP2 - DMI Port VC Capability Register 2 ...................................... 105
8.7.4 DMIPVCCTL - DMI Port VC Control........................................................... 106
8.7.5 DMIVC0RCAP - DMI VC0 Resource Capability ............................................ 106
8.7.6 DMIVC0RCTL0 - DMI VC0 Resource Control .............................................. 107
8.7.7 DMIVC0RSTS - DMI VC0 Resource Status................................................. 108
8.7.8 DMIVC1RCAP - DMI VC1 Resource Capability ............................................ 109
8.7.9 DMIVC1RCTL1 - DMI VC1 Resource Control .............................................. 109
8.7.10 DMIVC1RSTS - DMI VC1 Resource Status................................................. 111
8.7.11 DMIRCLDECH - DMI Root Complex Link Declaration................................... 112
8.7.12 DMI Element Self Description ................................................................. 112
8.7.13 DMILE1D - DMI Link Entry 1 Description .................................................. 113
8.7.14 DMILE1A - DMI Link Entry 1 Address ....................................................... 114
8.7.15 DMILE2D - DMI Link Entry 2 Description .................................................. 115
8.7.16 DMILE2A - DMI Link Entry 2 Address ....................................................... 116
8.7.17 DMIRCILCECH - DMI Root Complex Internal Link Control............................ 116
8.7.18 DMILCAP - DMI Link Capabilities ............................................................. 117
4
Datasheet
8.8
8.9
8.10
8.7.19 DMILCTL - DMI Link Control ................................................................... 118
8.7.20 DMILSTS - DMI Link Status.................................................................... 119
EPBAR ........................................................................................................... 119
8.8.1 EPESD - EP Element Self Description ....................................................... 120
8.8.2 EPLE1D - EP Link Entry 1 Description ...................................................... 121
8.8.3 EPLE1A - EP Link Entry 1 Address ........................................................... 122
8.8.4 EPLE2D - EP Link Entry 2 Description ...................................................... 122
8.8.5 EPLE2A - EP Link Entry 2 Address ........................................................... 123
PCI Device 2 Function 0 ................................................................................... 124
8.9.1 VID2 - Vendor Identification .................................................................. 126
8.9.2 DID - Device Identification..................................................................... 126
8.9.3 PCICMD2 - PCI Command...................................................................... 127
8.9.4 PCISTS2 - PCI Status............................................................................ 128
8.9.5 RID2 - Revision Identification................................................................. 129
8.9.6 CC - Class Code ................................................................................... 130
8.9.7 CLS - Cache Line Size ........................................................................... 130
8.9.8 MLT2 - Master Latency Timer ................................................................. 131
8.9.9 HDR2 - Header Type ............................................................................. 131
8.9.10 MMADR - Memory Mapped Range Address ............................................... 132
8.9.11 IOBAR - I/O Base Address ..................................................................... 132
8.9.12 GMADR – Graphics Memory Range Address.............................................. 133
8.9.13 GTTADR - Graphics Translation Table Range Address................................. 134
8.9.14 SVID2 - Subsystem Vendor Identification ................................................ 134
8.9.15 SID2 - Subsystem Identification ............................................................. 135
8.9.16 ROMADR - Video BIOS ROM Base Address ............................................... 135
8.9.17 CAPPOINT - Capabilities Pointer.............................................................. 136
8.9.18 INTRLINE - Interrupt Line ...................................................................... 136
8.9.19 INTRPIN - Interrupt Pin ......................................................................... 137
8.9.20 MINGNT - Minimum Grant ..................................................................... 137
8.9.21 MAXLAT - Maximum Latency .................................................................. 137
8.9.22 MGGC - Processor Graphics Control Register ............................................ 138
8.9.23 DEVEN - Device Enable ......................................................................... 139
8.9.24 SSRW - Software Scratch Read Write ...................................................... 140
8.9.25 BSM - Base of Stolen Memory ................................................................ 140
8.9.26 HSRW - Hardware Scratch Read Write ..................................................... 141
8.9.27 MC - Message Control ........................................................................... 141
8.9.28 MA - Message Address .......................................................................... 142
8.9.29 MD - Message Data............................................................................... 143
8.9.30 GDRST – Graphics Debug Reset ............................................................. 143
8.9.31 PMCAPID - Power Management Capabilities ID ......................................... 144
8.9.32 PMCAP - Power Management Capabilities ................................................. 144
8.9.33 PMCS - Power Management Control/Status .............................................. 145
8.9.34 SWSMI - Software SMI.......................................................................... 146
8.9.35 LBB - Legacy Backlight Brightness .......................................................... 147
8.9.36 ASLE – System Display Event Register .................................................... 147
8.9.37 ASLS – ASL Storage.............................................................................. 148
PCI Device 2 Function 1 ................................................................................... 149
8.10.1 VID2 - Vendor Identification .................................................................. 151
8.10.2 DID2 - Device Identification ................................................................... 151
8.10.3 PCICMD2 - PCI Command...................................................................... 152
8.10.4 PCISTS2 - PCI Status............................................................................ 153
8.10.5 RID2 - Revision Identification................................................................. 154
8.10.6 CC - Class Code Register ....................................................................... 155
Datasheet
5
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