TS4621E
High-performance class-G stereo headphone amplifier
with I
2
C volume control
Features
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TS4621EIJT - flip-chip
Power supply range: 2.3 V to 4.8 V
0.6 mA/channel quiescent current
2.1 mA current consumption with
100 µW/channel (10 dB crest factor)
0.006% typical THD+N at 1 kHz
100 dB typical PSRR at 217 Hz
100 dB of SNR A-weighted at G = 0 dB
Zero pop and click
I
2
C interface for volume control
Digital volume control range from -60 dB to
+4 dB
Independent right and left channel shutdown
control
Integrated high-efficiency buck converter
Low software standby current: 5 µA max
Output-coupling capacitors removed
Thermal shutdown and short-circuit protection
Flip-chip package: 1.65 mm x 1.65 mm,
400 µm pitch, 16 bumps
When powered by a battery, the buck converter
generates the appropriate voltage to the amplifier
depending on the amplitude of the audio signal to
supply the headsets. It achieves a total 2.1 mA
current consumption at 100 µW output power
(10 dB crest factor).
THD+N is 0.02% maximum at 1 kHz and PSRR is
100 dB at 217 Hz, which ensures a high audio
quality of the device in a wide range of
environments.
The traditionally bulky output coupling capacitors
can be removed.
A dedicated common-mode sense pin removes
parasitic ground noise.
The TS4621E is designed to be used with an
output serial resistor. It ensures unconditional
stability over a wide range of capacitive loads.
The TS4621E is packaged in a tiny 16-bump
flip-chip package with a pitch of 400 µm.
INR+
CMS
PVSS
C2
INR-
VOUTR
SCL
SDA
Pinout (top view)
D
C
INL+
HPVDD
C1
AGND
B
INL-
VOUTL
AVDD
SW
A
4
3
2
1
Balls are underneath
Applications
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Cellular phones, smart phones
Mobile internet devices
PMP/MP3 players
Description
The TS4621E is a class-G stereo headphone
driver dedicated to high audio performance, high
power efficiency and space-constrained
applications.
It is based on the core technology of a low power
dissipation amplifier combined with a high-
efficiency buck converter for supplying this
amplifier.
September 2011
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Contents
TS4621E
Contents
1
2
3
4
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
Typical application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
I
2
C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.1
4.1.2
4.1.3
I²C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Control register CR2 - address 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Control register CR1 - address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2
4.3
Wake-up and standby time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Common mode sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
6
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
Doc ID 022201 Rev 1
TS4621E
Absolute maximum ratings and operating conditions
1
Absolute maximum ratings and operating conditions
Table 1.
Symbol
V
CC
V
in+
,V
in-
T
stg
T
j
R
thja
P
d
Absolute maximum ratings
Parameter
Supply voltage
(1)
during 1ms.
Input voltage referred to ground
Storage temperature
Maximum junction temperature
(2)
Thermal resistance junction to ambient
(3)
Power dissipation
Human body model (HBM)
(5)
All pins
VOUTR, VOUTL vs. AGND
Machine model (MM), min. value
(6)
Value
5.5
+/- 1.2
-65 to +150
150
200
Internally limited
(4)
2
4
100
500
750
+/- 8
+/- 15
200
260
kV
V
V
Unit
V
V
°C
°C
°C/W
ESD
Charge device model (CDM)
All pins
VOUTR, VOUTL
IEC61000-4-2 level 4, contact
(7)
IEC61000-4-2 level 4, air discharge
(7)
kV
mA
°C
Latch-up
Latch-up immunity
Lead temperature (soldering, 10 sec)
1. All voltage values are measured with respect to the ground pin.
2. Thermal shutdown is activated when maximum junction temperature is reached.
3. The device is protected from over-temperature by a thermal shutdown mechanism, active at 150° C.
4. Exceeding the power derating curves for long periods may provoke abnormal operation.
5. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
6. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5
Ω).
This is done for all couples of
connected pin combinations while the other pins are floating.
7. The measurement is performed on an evaluation board, with ESD protection EMIF02-AV01F3.
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Absolute maximum ratings and operating conditions
Table 2.
Symbol
V
CC
HPVDD
SDA, SCL
R
L
C
L
T
oper
R
thja
Supply voltage
Buck DC output voltages
High rail voltage
Low rail voltage
Input voltage range
Load resistor
Load capacitor
Serial resistor of 12
Ω
minimum, R
L
≥
16
Ω
Operating free air temperature range
Flip-chip thermal resistance junction to ambient
TS4621E
Operating conditions
Parameter
Value
2.3 to 4.8
1.9
1.2
GND to V
cc
≥
16
0.8 to 100
-40 to +85
90
Unit
V
V
V
Ω
nF
°C
°C/W
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Doc ID 022201 Rev 1
TS4621E
Typical application schematics
2
Typical application schematics
Figure 1.
Typical application schematics for the TS4621E
Vbat
Cs
2.2
uF
AVdd
Positive
supply
Cin
2.2
uF
InL-
-
InL+
Level
detector
VoutL
Sw
HpVdd
Ct
10
uF
Rout
12 ohms min.
CMS
InR+
InR-
Cin
2.2
uF
SDA
SCL
-
Level
detector
VoutR
Rout
12 ohms min.
Cout
0.8 nF min.
+
3
2
1
J1
Cout
0.8 nF min.
L1
3.3 uH
Negative left input
Positive left input
Cin
2.2
uF
Cin
2.2
uF
+
Negative right input
Positive right input
I2C
PVss
Negative
supply
C1
C2
C12
2.2
uF
AGnd
I²C
bus
Css
2.2
uF
AM06119
Table 3.
TS4621E pin description
Pin name
SW
AVDD
VOUTL
INL-
AGND
C1
HPVDD
INL+
C2
PVSS
CMS
INR+
SDA
SCL
VOUTR
INR-
Pin definition
Switching node of the buck converter
Analog supply voltage, connect to battery
Output signal for left audio channel
Negative input signal for left audio channel
Device ground
Flying capacitor terminal for internal negative supply generator
Buck converter output, power supply for amplifier
Positive input signal for left audio channel
Flying capacitor terminal for internal negative supply generator
Negative supply generator output
Common mode sense, to be connected as close as possible to the
ground of headphone/line out plug
Positive input signal for right audio channel
I²C data signal, up to V
CC
tolerant input
I²C clock signal, up to V
CC
tolerant input
Output signal for right audio channel
Negative input signal for right audio channel
Pin number
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
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