DATASHEET
ISL62771
Multiphase PWM Regulator for AMD Fusion™ Mobile CPUs Using SVI 2.0
The
ISL62771
is fully compliant with AMD Fusion SVI 2.0 and
provides a complete solution for microprocessor and graphics
processor core power. The ISL62771 controller supports two
Voltage Regulators (VRs) with three integrated gate drivers. The
Core VR supports 2-, or 1-phase configurations while the
Northbridge VR supports 1-phase operation. The two VRs share a
serial control bus to communicate with the AMD CPU and achieve
lower cost and smaller board area compared with two-chip
solutions.
The PWM modulator is based on Intersil’s Robust Ripple
Regulator R3™ Technology. Compared to traditional modulators,
the R3 modulator can automatically change switching frequency
for faster transient settling time during load transients and
improved light-load efficiency.
The ISL62771 has several other key features. Both outputs
support DCR current sensing with single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. Both outputs utilize remote voltage sense, adjustable
switching frequency, OC protection and power-good.
FN8321
Rev 4.00
November 18, 2015
Features
• Supports AMD SVI 2.0 serial data bus interface
- Serial VID clock frequency range 100kHz to 25MHz
• Dual output controller with integrated drivers
• Precision voltage regulation
- 0.5% system accuracy over-temperature
- 0.5V to 1.55V in 6.25mV steps
- Enhanced load line accuracy
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Programmable 1- or 2-phase for the core output
• Adaptive body diode conduction time reduction
• Superior noise immunity and transient response
• Output current and voltage telemetry
• Differential remote voltage sensing
• High efficiency across entire load range
• Programmable VID offset and droop on both outputs
• Programmable switching frequency for both outputs
• Excellent dynamic current balance between phases
• Protection: OCP/WOC, OVP, PGOOD and thermal monitor
• Small footprint 40 Ld 5x5 TQFN package
- Pb-free (RoHS compliant)
Applications
• AMD fusion CPU/GPU and APU core power
• Notebook computers
Related Literature
•
TB497,
“Disabling the North Bridge Regulator on the
ISL62771”
Core Performance
100
90
80
EFFICIENCY (%)
70
60
50
40
30
20
10
0
0
5
10
15
20
V
OUT
CORE = 1.1V
25 30 35
I
OUT
(A)
40
45
50
55
V
IN
= 19V
V
IN
= 12V
V
IN
= 8V
V
OUT
(A)
1.12
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0
V
OUT
CORE = 1.1V
5
10
15
20
25
30
35
40
45
50
55
I
OUT
(A)
V
IN
= 12V
V
IN
= 19V
V
IN
= 8V
FIGURE 1. EFFICIENCY vs LOAD
FIGURE 2. V
OUT
vs LOAD
FN8321 Rev 4.00
November 18, 2015
Page 1 of 35
ISL62771
Table of Contents
Simplified Application Circuit for Mid-Power CPUs . . . . . . . 4
Simplified Application Circuit for Low Power CPUs [1+1
Con-figuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Simplified Application Circuit for Low Power CPUs [1+1
Con-figuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .11
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Recommended Operating Conditions . . . . . . . . . . . . . . . . .11
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .13
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . 15
Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage Regulation and Load Line Implementation . . . . . . . 16
Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Adaptive Body Diode Conduction Time Reduction . . . . . . . . 19
Resistor Configuration Options. . . . . . . . . . . . . . . . . . . . . . .19
VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-PWROK Metal VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . .
SVI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Offset Trim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitor [NTC, NTC_NB]. . . . . . . . . . . . . . . . . . . . . . .
Fault Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . .
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitor Component Selection . . . . . . . . . . . . . . . . .
20
20
20
20
21
21
23
23
23
24
24
24
25
25
25
25
26
26
26
26
28
28
29
29
30
30
Telemetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FN8321 Rev 4.00
November 18, 2015
Page 2 of 35
FPGA/CPLD
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