a
FEATURES
Ultrahigh Speed: Current Settling to 1 LSB in 35 ns
High Stability Buried Zener Reference on Chip
Monotonicity Guaranteed Over Temperature
10.24 mA Full-Scale Output Suitable for Video
Applications
Integral and Differential Linearity Guaranteed Over
Temperature
0.3" “Skinny DIP” Packaging
Variable Threshold Allows TTL and CMOS
Interface
MIL-STD-883 Compliant Versions Available
12-Bit Ultrahigh Speed
Monolithic D/A Converter
AD568
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD568 is an ultrahigh-speed, 12-bit digital-to-analog con-
verter (DAC) settling to 0.025% in 35 ns. The monolithic de-
vice is fabricated using Analog Devices’ Complementary Bipolar
(CB) Process. This is a proprietary process featuring high-speed
NPN and PNP devices on the same chip without the use of di-
electric isolation or multichip hybrid techniques. The high speed
of the AD568 is maintained by keeping impedance levels low
enough to minimize the effects of parasitic circuit capacitances.
The DAC consists of 16 current sources configured to deliver a
10.24 mA full-scale current. Multiple matched current sources
and thin-film ladder techniques are combined to produce bit
weighting. The DAC’s output is a 10.24 mA full scale (FS) for
current output applications or a 1.024 V FS unbuffered voltage
output. Additionally, a 10.24 V FS buffered output may be gen-
erated using an onboard 1 kΩ span resistor with an external op
amp. Bipolar ranges are accomplished by pin strapping.
Laser wafer trimming insures full 12-bit linearity. All grades of
the AD568 are guaranteed monotonic over their full operating
temperature range. Furthermore, the output resistance of the
DAC is trimmed to 100
Ω ±
1.0%. The gain temperature coeffi-
cient of the voltage output is 30 ppm/°C max (K).
The AD568 is available in three performance grades. The
AD568JQ and KQ are available in 24-pin cerdip (0.3") packages
and are specified for operation from 0°C to +70°C. The
AD568SQ features operation from –55°C to +125°C and is also
packaged in the hermetic 0.3" cerdip.
PRODUCT HIGHLIGHTS
1. The ultrafast settling time of the AD568 allows leading edge
performance in waveform generation, graphics display and
high speed A/D conversion applications.
2. Pin strapping provides a variety of voltage and current output
ranges for application versatility. Tight control of the abso-
lute output current reduces trim requirements in externally-
scaled applications.
3. Matched on-chip resistors can be used for precision scaling in
high speed A/D conversion circuits.
4. The digital inputs are compatible with TTL and +5 V
CMOS logic families.
5. Skinny DIP (0.3") packaging minimizes board space require-
ments and eases layout considerations.
6. The AD568 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD568/883B data sheet for detailed
specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD568* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/27/2017
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DESIGN RESOURCES
•
AD568 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DOCUMENTATION
Data Sheet
•
AD568: 12-Bit Ultrahigh Speed Monolithic D/A Converter
Data Sheet
•
AD568: Military Data Sheet
DISCUSSIONS
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REFERENCE MATERIALS
Solutions Bulletins & Brochures
•
Digital to Analog Converters ICs Solutions Bulletin
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AD568–SPECIFICATIONS
(@ = +25 C, V , V
CC
EE
=
15 V unless otherwise noted)
Min
12
AD568S
Typ
Max
Units
Bits
LSB
LSB
LSB
LSB
% of FSR
% of FSR
% of FSR
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
Model
Min
RESOLUTION
ACCURACY
Linearity
T
MIN
to T
MAX
Differential Nonlinearity
T
MIN
to T
MAX
Monotonicity
Unipolar Offset
Bipolar Offset
Bipolar Zero
Gain Error
TEMPERATURE COEFFICIENTS
2
Unipolar Offset
Bipolar Offset
Bipolar Zero
Gain Drift
Gain Drift (I
OUT
)
DATA INPUTS
Logic Levels (T
MIN
to T
MAX
)
V
IH
V
IL
Logic Currents (T
MIN
to T
MAX
)
I
IH
I
IL
V
TH
Pin Voltage
CODING
CURRENT OUTPUT RANGES
VOLTAGE OUTPUT RANGES
COMPLIANCE VOLTAGE
OUTPUT RESISTANCE
Exclusive of R
L
Inclusive of R
L
SETTLING TIME
Current to
±
0.025%
±
0.1%
Voltage
50
Ω
Load
3
, 0.512 V p-p,
to 0.025%
to 0.1%
to 1%
75
Ω
Load
3
, 0.768 V p-p,
to 0.025%
to 0.1%
to 1%
100
Ω
(Internal R
L
)
3
, 1.024 V p-p,
to 0.025%
to 0.1%
to 1%
Glitch Impulse
4
Peak Amplitude
FULL-SCALE TRANSlTlON
5
10% to 90% Rise Time
90% to 10% Fall Time
POWER REQUIREMENTS
+13.5 V to +16.5 V
–13.5 V to –16.5 V
Power Dissipation
PSRR
TEMPERATURE RANGE
Rated Specification
2
Storage
0
–65
–2
160
99
1
AD568J
Typ
Max
Min
12
AD568K
Typ
Max
12
–1/2
+1/2
–1/4
+1/4
–1/2
+1/2
–3/4
+3/4
–1/2
+1/2
–3/4
+3/4
–1
+1
–1/2
+1/2
–1
+1
–1
+1
–1
+1
–1
–1
GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
–0.2
+0.2
*
*
*
*
–1.0
+1.0
*
*
*
*
–0.2
+0.2
*
*
*
*
–1.0
+1.0
*
*
*
*
–5
–30
–15
–50
–150
+5
+30
+15
+50
+150
–3
–20
•
–30
*
+3
+20
•
+30
*
–5
–30
•
–50
*
+5
+30
•
+50
*
2.0
0.0
–10
–0.5
0
–60
1.4
7.0
0.8
+10
–100
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–100
*
*
*
*
–200
V
V
µA
µA
V
BINARY, OFFSET BINARY
0 to 10.24,
±
5.12
0 to 1.024,
±
0.512
+1.2
200
100
240
101
*
*
*
*
*
*
*
*
mA
V
V
Ω
Ω
35
23
*
*
*
*
ns to 0.025% of FSR
ns to 0.1% of FSR
37
25
18
40
25
20
50
38
24
350
15
11
11
27
–7
525
32
–8
625
0.05
+70
+150
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
+70
*
–55
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
+125
*
ns to 0.025% of FSR
ns to 0.1% of FSR
ns to 1% of FSR
ns to 0.025% of FSR
ns to 0.1% of FSR
ns to 1% of FSR
ns to 0.025% of FSR
ns to 0.1% of FSR
ns to 1% of FSR
pV-sec
% of FSR
ns
ns
mA
mA
mW
% of FSR/V
°C
°C
NOTES
*Same as AD568J.
1
Measured in I
OUT
mode.
2
Measured in V
OUT
mode, unless otherwise specified. See text for further information.
3
Total Resistance. Refer to Figure 3,
4
At the major carry, driven by HCMOS logic. See text for further explanation.
5
Measured in V
OUT
mode.
Specifications shown in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
–2–
REV. A
AD568
LSB
12
11
10
9
8
7
6
5
4
3
2
MSB
1
24
PIN CONFIGURATION
V
CC
BURIED
ZENER
REFERENCE
23
PNP
CURRENT
SOURCES
PNP
SWITCHES
13
2X
4X
THRESHOLD
CONTROL
1.4V
BAND-
GAP
REF
THRESHOLD
COMMON
LADDER
COMMON
14
I
OUT
THIN-FILM R-2R LADDER
(100 - 200Ω)
20
200Ω
19
21
REFERENCE
COMMON
I
OUT
LOAD RESISTOR
(R
L
)
BIPOLAR
OFFSET (I
BPO
)
10V SPAN
RESISTOR
10V SPAN
RESISTOR
17
DIFFUSED R-2R LADDER
(10 - 20Ω)
I
OUT
BIPOLAR
CURRENT
GENERATOR
18
22
15
1kΩ
16
AD568
ANALOG
COMMON
V
EE
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS
1
V
CC
to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
V
EE
to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
REFCOM to LCOM . . . . . . . . . . . . . . . . . +100 mV to –10 V
ACOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
100 mV
THCOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . .
±
500 mV
SPANs to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
12 V
I
BPO
to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
5 V
I
OUT
to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to V
TH
Digital Inputs to THCOM . . . . . . . . . . . . . –500 mV to +7.0 V
Voltage Across Span Resistor . . . . . . . . . . . . . . . . . . . . . . 12 V
V
TH
to THCOM . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +1.4 V
Logic Threshold Control Input Current . . . . . . . . . . . . . 5 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mW
Storage Temperature Range
Q (Cerdip) Package . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Thermal Resistance
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
θ
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C/W
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
l
Package Option
2
Temperature
Range C
0 to +70
0 to +70
–55 to +125
Linearity
Error Max
@ 25 C
±
1/2
±
1/4
±
1/2
Voltage
Gain T.C.
Max ppm/ C
±
50
±
30
±
50
AD568JQ
AD568KQ
AD568SQ
24-Lead Cerdip (Q-24)
24-Lead Cerdip (Q-24)
24-Lead Cerdip (Q-24)
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices
Military Products Databook or current AD568/883B data sheet.
2
Q = Cerdip.
Definitions
LINEARITY ERROR (also called INTEGRAL NONLINEAR-
ITY OR INL): Analog Devices defines linearity error as the
maximum deviation of the actual analog output from the ideal
output (a straight line drawn from 0 to FS) for any bit combina-
tion expressed in multiples of 1 LSB. The AD568 is laser
trimmed to 1/4 LSB (0.006% of FS) maximum linearity error at
+25°C for the K version and 1/2 LSB for the J and S versions.
DIFFERENTIAL LINEARITY ERROR (also called DIFFER-
ENTIAL NONLINEARITY or DNL): DNL is the measure of
the variation in analog value, normalized to full scale, associated
with a 1 LSB change in digital input code. Monotonic behavior
requires that the differential linearity error not exceed 1 LSB in
the negative direction.
MONOTONICITY: A DAC is said to be monotonic if the out-
put either increases or remains constant as the digital input
increases.
UNIPOLAR OFFSET ERROR: The deviation of the analog
output from the ideal (0 V or 0 mA) when the inputs are set to
all 0s is called unipolar offset error.
BIPOLAR OFFSET ERROR: The deviation of the analog out-
put from the ideal (negative half-scale) when the inputs are set
to all 0s is called bipolar offset error.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD568 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD568
BIPOLAR ZERO ERROR: The deviation of the analog output
from the ideal half-scale output of 0 V (or 0 mA) for bipolar
mode when only the MSB is on (100 . . .00) is called bipolar
zero error.
GAIN ERROR: The difference between the ideal and actual
output span of FS –1 LSB, expressed in % of FS, or LSB, when
all bits are on.
GLITCH IMPULSE: Asymmetrical switching times in a DAC
give rise to undesired output transients which are quantified by
their glitch impulse. It is specified as the net area of the glitch in
nV-sec or pA-sec.
COMPLIANCE VOLTAGE: The range of allowable voltage at
the output of a current-output DAC which will not degrade the
accuracy of the output current.
SETTLING TIME: The time required for the output to reach
and remain within a specified error band about its final value,
measured from the digital input transition.
+15V
0.8
–15V
0.2µF
0.1µF
1
+15V 24
REFCOM 23
–15V 22
I
BPO
21
I
OUT
20
0.1µF
0.1µF
OUTPUT – VOLTS
0.6
2
3
4
5
FERRITE BEADS
STACKPOLE 57-1392
OR
AMIDON FB-43B-101
OR EQUIVALENT
0.4
DIGITAL
INPUTS
6
7
8
9
10
AD568
R
L
19
ANALOG
OUTPUT
R
EXT
(OPTIONAL)
ACOM 18
LCOM 17
SPAN 16 NC
SPAN 15 NC
THCOM 14
VTH 13
R
TH
1kΩ
100pF
ANALOG
SUPPLY GROUND
ANALOG
GND PLANE
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
0
50
100
150
TIME – ns
200
250
11
12
Figure 2. Glitch Impulse
Connecting the AD568
UNBUFFERED VOLTAGE OUTPUT
Unipolar Configuration
+5V
Figure 3. Unipolar Output Unbuffered 0 V to +1.024 V
+15V
–15V
0.2µF
0.1µF
1
2
3
4
5
DIGITAL
INPUTS
6
7
8
9
10
11
12
+15V 24
REFCOM 23
–15V 22
I
BPO
21
I
OUT
20
0.1µF
0.1µF
Figure 3 shows the AD568 configured to provide a unipolar 0 to
+1.024 V output range. In this mode, the bipolar offset termi-
nal, Pin 21, should be grounded if not used for offset trimming.
The nominal output impedance of the AD568 with Pin 19
grounded has been trimmed to 100
Ω, ±
1%. Other output im-
pedances can be generated with an external resistor, R
EXT
, be-
tween Pins 19 and 20. An R
EXT
equalling 300
Ω
will yield a
total output resistance of 75
Ω,
while an R
EXT
of 100
Ω
will pro-
vide 50
Ω
of output resistance. Note that since the full-scale
output current of the DAC remains 10.24 mA, changing the
load impedance changes the unbuffered output voltage accord-
ingly. Settling time and full-scale range characteristics for these
load impedances are provided in the specifications table.
Bipolar Configuration
AD568
R
L
19
ANALOG
OUTPUT
ANALOG
SUPPLY
GROUND
ACOM 18
LCOM 17
SPAN 16
SPAN 15
THCOM 14
VTH 13
100pF
DIGITAL
GND PLANE
ANALOG
GND PLANE
DIGITAL
SUPPLY
GROUND
Figure 4 shows the connection scheme used to provide a bipolar
output voltage range of 1.024 V. The bipolar offset (–0.512 V)
occurs when all bits are OFF (00 . . . 00), bipolar zero (0 V) oc-
curs when the MSB is ON with all other bits OFF (10 . . . 00),
and full-scale minus 1 LSB (0.51175 V) is generated when all
bits are ON (11 . . . 11). Figure 5 shows an optional bipolar
mode with a 2.048 V range. The scale factor in this mode will
not be as accurate as the configuration shown in Figure 4, be-
cause the laser-trimmed resistor R
L
is not used.
–4–
+5V
Figure 4. Bipolar Output Unbuffered
±
0.512 V
Figure 4 also demonstrates how the internal span resistor may
be used to bias the V
TH
pin (Pin 13) from a 5 V supply. This
eliminates the requirement for an external R
TH
in applications
that do not require the precision span resistor.
REV. A
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