DATASHEET
ISL78302A
Dual LDO with Low Noise, Very High PSRR and Low IQ
ISL78302A
is a high-performance dual LDO capable of
sourcing 300mA current from each output. It has a low
standby current and very high PSRR and is stable with output
capacitance of 1µF to 10µF with ESR of up to 200mΩ.
The device integrates an individual Power-On Reset (POR)
function for each output. The POR delay for VO2 can be
externally programmed by connecting a timing capacitor to the
CPOR pin. The POR delay for VO1 is internally fixed at
approximately 2ms. A reference bypass pin is also provided for
connecting a noise-filtering capacitor for low noise and
high-PSRR applications.
The quiescent current is typically only 47µA with both LDOs
enabled and active. Separate Enable pins control each
individual LDO output. When both Enable pins are low, the
device is in shutdown, typically drawing less than 0.3µA.
The ISL78302A is AEC-Q100 qualified. The ISL78302A is rated
for the automotive temperature range (-40°C to +105°C).
FN7932
Rev 2.00
December 22, 2015
Features
• Integrates Two 300mA High-performance LDOs
• Excellent Transient Response to Large Current Steps
• ±1.8% Accuracy Over All Operating Conditions
• Excellent Load Regulation: < 0.1% Voltage Change Across
Full Range of Load Current
• Low Output Noise: Typically 30µV
RMS
at 100µA (1.5V)
• Very High PSRR: 90dB at 1kHz
• Extremely Low Quiescent Current: 47µA (Both LDOs Active)
• Wide Input Voltage Capability: 2.3V to 6.5V
• Low Dropout Voltage: Typically 230mV at 300mA
• Stable with 1µF to 10µF Ceramic Capacitors
• Separate Enable and POR Pins for Each LDO
• Soft-start and Staged Turn-on to Limit Input Current Surge
During Enable
• Current Limit and Overheat Protection
• Tiny 10 Ld 3mmx3mm DFN Package
• -40°C to +105°C Operating Temperature Range
• Pb-free (RoHS Compliant)
• AEC-Q100 Qualified
Applications
• Radio Receivers
• Camera Modules
• GPS/Navigation
• Infotainment Systems
ISL78302A
VIN (2.3 TO 6.5V)
1
ON
2
3
4
5
C1
C2
C3
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR2
POR1
GND
10
9
8
7
6
C4
C5
V
OUT2
OK
V
OUT2
TOO LOW
V
OUT1
OK
V
OUT1
TOO LOW
V
OUT1
V
OUT2
RESET2
(200ms DELAY,
C3 = 0.01µF)
RESET1
(2ms DELAY)
ENABLE1
OFF ON
ENABLE2
OFF
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
C3: 0.01µF X7R CERAMIC CAPACITOR
FIGURE 1. TYPICAL APPLICATION
FN7932 Rev 2.00
December 22, 2015
Page 1 of 12
ISL78302A
Block Diagram
VIN
VO1
VO2
LDO
ERROR
AMPLIFIER
~1.0V
VREF
TRIM
POR
COMPARATOR
1V
VOK1
POR1
LDO-2
QEN1
QEN2
VOK2
POR2
VO1
VO2
IS1
LDO-1
QEN1
IS1
IS2
VO2
100k
EN1
EN2
CBYP
UVLO
CONTROL
LOGIC
POR2
VOK2
POR2
DELAY
100k
BANDGAP AND
TEMPERATURE
SENSOR
VO1
VOLTAGE
REFERENCE
GENERATOR
1.00V
0.94V
0.90V
VOK1
POR1
DELAY
POR1
CPOR
GND
FN7932 Rev 2.00
December 22, 2015
Page 2 of 12
ISL78302A
Pin Configuration
ISL78302A
(10 LD 3X3 DFN)
TOP VIEW
VIN 1
EN1 2
EN2 3
CBYP 4
CPOR 5
10 VO1
9
8
7
6
VO2
POR2
POR1
GND
Pin Descriptions
PIN NUMBER PIN NAME
1
2
3
4
5
VIN
EN1
EN2
CBYP
CPOR
TYPE
Analog I/O
DESCRIPTION
Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.
Low Voltage Compatible CMOS Input LDO-1 Enable
Low Voltage Compatible CMOS Input LDO-2 Enable
Analog I/O
Analog I/O
Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01µF to 1µF
between this pin and GND to tune in the desired noise and PSRR performance.
POR2 Delay Setting Capacitor Pin. Connect a capacitor between this pin and GND to
delay the POR2 output release after LDO-2 output reaches 94% of its specified
voltage level (200ms delay per 0.01µF).
Connection to system ground. Connect to PCB Ground plane.
Open-drain POR Output for LDO-1 (active-low). Internally connected to VO1 through
100kΩ resistor.
Open-drain POR Output for LDO-2 (active-low). Internally connected to VO2 through
100kΩ resistor.
LDO-2 Output. Connect capacitor of value 1µF to 10µF to GND
(1µF recommended).
LDO-1 Output. Connect capacitor of value 1µF to 10µF to GND
(1µF recommended).
6
7
8
9
10
GND
POR1
POR2
VO2
VO1
Ground
Open Drain Output (1mA)
Open Drain Output (1mA)
Analog I/O
Analog I/O
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL78302AARMMZ
ISL78302AARLLZ
ISL78302AARJMZ
ISL78302AARJRZ
ISL78302AARJCZ
ISL78302AARGCZ
ISL78302AARPLZ
ISL78302AARBJZ
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL78302A.
For more information on MSL, please see Tech Brief
TB363.
PART
MARKING
DNAL
DNAM
DNAN
DNAP
DNAK
DNAR
DNAS
DNAT
VO1 VOLTAGE
(V)
3.0
2.9
2.8
2.8
2.8
2.7
1.85
1.5
VO2 VOLTAGE
(V)
3.0
2.9
3.0
2.6
1.8
1.8
2.9
2.8
TEMP RANGE
(°C)
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
PACKAGE
(RoHS Compliant)
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
PKG DWG. #
L10.3x3C
L10.3x3C
L10.3x3C
L10.3x3C
L10.3x3C
L10.3x3C
L10.3x3C
L10.3x3C
FN7932 Rev 2.00
December 22, 2015
Page 3 of 12
ISL78302A
Absolute Maximum Ratings
Supply Voltage (V
IN
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.1V
V
O
1, V
O
2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V
IN
+ 0.3)V
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
10 Ld 3x3 DFN Package (Notes
4, 5).
. . . .
59
18.5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
ESD Ratings
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3000V
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per AEC-Q100-011) . . . . . . . . . . . . . . 1500V
Recommended Operating Conditions
Ambient Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -40°C to 105°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF;
CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +105°C.
PARAMETER
DC CHARACTERISTICS
Supply Voltage
Ground Current
I
DD1
I
DD2
Shutdown Current
UVLO Threshold
I
DDS
V
UV+
V
UV-
Regulation Voltage Accuracy
V
IN
= V
O
+ 0.5V to 5.5V, I
O
= 10µA to 300mA, T
J
= +25°C
V
IN
= V
O
+ 0.5V to 5.5V, I
O
= 10µA to 300mA, T
J
= -40°C to +125°C
Maximum Output Current
Internal Current Limit
Dropout Voltage (Note
7)
I
MAX
I
LIM
V
DO1
V
DO2
V
DO3
Thermal Shutdown Temperature
T
SD+
T
SD-
AC CHARACTERISTICS
Ripple Rejection
I
O
= 10mA, V
IN
= 2.8V(min), V
O
= 1.8V, C
BYP
= 0.1µF
@ 1kHz
@ 10kHz
@ 100kHz
90
70
50
dB
dB
dB
I
O
= 300mA; V
O
2.5V
I
O
= 150mA; V
O
2.5V
I
O
= 300mA; 2.5V
V
O
2.8V
I
O
= 150mA; 2.5V
V
O
2.8V
I
O
= 300mA; V
O
> 2.8V
I
O
= 150mA; V
O
> 2.8V
Continuous
1.9
1.6
-0.8
-1.8
300
320
475
450
225
250
125
230
115
145
110
145
160
250
mV
mV
mV
mV
°C
°C
650
V
IN
Quiescent condition: I
O1
= 0µA; I
O2
= 0µA
One LDO active
Both LDO active
30
47
0.3
2.1
1.8
36
55
2.1
2.3
2.0
+0.8
+1.8
µA
µA
µA
V
V
%
%
mA
mA
mV
2.3
6.5
V
SYMBOL
TEST CONDITIONS
MIN
(Note
6)
TYP
MAX
(Note
6)
UNITS
Electrical Specifications
FN7932 Rev 2.00
December 22, 2015
Page 4 of 12
ISL78302A
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -40°C to 105°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF;
CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) (Continued)
PARAMETER
Output Noise Voltage
DEVICE START-UP CHARACTERISTICS
Device Enable Time
LDO Soft-Start Ramp Rate
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage
Input High Voltage
Input Leakage Current
Pin Capacitance
POR1, POR2 PIN CHARACTERISTICS
POR1, POR2 Thresholds
V
POR+
V
POR-
POR1 Delay
t
P1LH
t
P1HL
POR2 Delay
t
P2LH
t
P2HL
POR1, POR2 Pin Output Low
Voltage
POR1, POR2 Pin Internal Pull-Up
Resistance
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. VOx = 0.98*VOx(NOM); valid for VOx greater than 1.85V.
V
OL
R
POR
@ I
OL
= 1.0mA
78
100
C
POR
= 0.01µF
100
As a percentage of nominal output voltage
91
87
0.5
94
90
2.0
25
200
25
0.2
180
300
97
93
3.2
%
%
ms
µs
ms
µs
V
kΩ
V
IL
V
IH
I
IL
, I
IH
C
PIN
Informative
5
-0.3
1.35
0.5
V
IN
+
0.3
0.1
V
V
µA
pF
t
EN
t
SSR
Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VO (nom)
Slope of linear portion of LDO output voltage ramp during start-up
250
30
500
60
µs
µs/V
SYMBOL
TEST CONDITIONS
I
O
= 100µA, V
O
= 1.5V, T
A
= +25°C, C
BYP
= 0.1µF
BW = 10Hz to 100kHz
MIN
(Note
6)
TYP
30
MAX
(Note
6)
UNITS
µV
RMS
Electrical Specifications
EN1
EN2
t
EN
V
POR+
V
POR-
V
POR+
<t
P1HL
VO1
VO2
<t
P2HL
t
P1LH
t
P2LH
POR1
POR2
t
P1HL
t
P2HL
V
POR-
FIGURE 2. TIMING PARAMETER DEFINITION
FN7932 Rev 2.00
December 22, 2015
Page 5 of 12
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