CY62128EV30 MoBL
®
1-Mbit (128K × 8) Static RAM
1-Mbit (128K × 8) Static RAM
Features
■
■
Functional Description
The CY62128EV30 is a high performance CMOS static RAM
module organized as 128K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE
1
HIGH or CE
2
LOW). The
eight input and output pins (I/O
0
through I/O
7
) are placed in a
high impedance state when the device is deselected (CE
1
HIGH
or CE
2
LOW), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE
1
LOW and CE
2
HIGH and WE
LOW).
To write to the device, take chip enable (CE
1
LOW and CE
2
HIGH) and write enable (WE) inputs LOW. Data on the eight I/O
pins is then written into the location specified on the address pin
(A
0
through A
16
).
To read from the device, take chip enable (CE
1
LOW and CE
2
HIGH) and output enable (OE) LOW while forcing write enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
For a complete list of related resources,
click here.
Very high speed: 45 ns
Temperature ranges:
❐
Industrial: –40 °C to +85 °C
Wide voltage range: 2.2 V to 3.6 V
Pin compatible with CY62128DV30
Ultra low standby power
❐
Typical standby current: 1 µA
❐
Maximum standby current: 4 µA
Ultra low active power
❐
Typical active current: 1.3 mA at f = 1 MHz
Easy memory expansion with CE
1
, CE
2,
and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Offered in Pb-free 32-pin small outline integrated circuit (SOIC),
32-pin thin small outline package (TSOP) Type I, and 32-pin
shrunk thin small outline package (STSOP) packages
■
■
■
■
■
■
■
■
Logic Block Diagram
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
WE
OE
INPUT BUFFER
I/O 0
I/O 1
SENSE AMPS
ROW DECODER
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
128K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
I/O 7
A12
A14
A13
A16
A15
Cypress Semiconductor Corporation
Document Number: 38-05579 Rev. *O
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 24, 2017
CY62128EV30 MoBL
®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC
®
Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-05579 Rev. *O
Page 2 of 19
CY62128EV30 MoBL
®
Pin Configuration
Figure 1. 32-pin STSOP pinout
[1]
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
25
26
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Figure 2. 32-pin TSOP I pinout
[1]
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Top View
(not to scale)
Top View
(not to scale)
Figure 3. 32-pin SOIC pinout
[1]
Top View
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
Product Portfolio
Power Dissipation
Product
Range
Min
CY62128EV30LL Industrial
2.2
V
CC
Range (V)
Typ
[2]
3.0
Max
3.6
45
Speed
(ns)
Typ
[2]
1.3
Operating I
CC
(mA)
f = 1 MHz
Max
2.0
11
f = f
max
Typ
[2]
Max
16
Standby I
SB2
(µA)
Typ
[2]
1
Max
4
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
Document Number: 38-05579 Rev. *O
Page 3 of 19
CY62128EV30 MoBL
®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential
[3, 4]
...............–0.3 V to V
CC(max)
+ 0.3 V
DC voltage applied to outputs
in high Z State
[3, 4]
......................–0.3 V to V
CC(max)
+ 0.3 V
DC input voltage
[3, 4]
...................–0.3 V to V
CC(max)
+ 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................. > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
V
CC
[5]
CY62128EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1[7]
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
V
CC
operating supply current
Test Conditions
I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70 V
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
> 2.70 V
V
CC
= 2.2 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.2 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
GND < V
I
< V
CC
GND < V
O
< V
CC
, output disabled
f = f
max
= 1/t
RC
f = 1 MHz
Automatic CE power-down
current – CMOS inputs
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
45 ns (Industrial)
Min
2.0
2.4
–
–
1.8
2.2
–0.3
–0.3
–1
–1
–
–
–
Typ
[6]
–
–
–
–
–
–
–
–
–
–
11
1.3
1
Max
–
–
0.4
0.4
V
CC
+ 0.3 V
V
CC
+ 0.3 V
0.6
0.8
+1
+1
16
2.0
4
Unit
V
V
V
V
V
V
V
V
µA
µA
mA
mA
µA
CE
1
> V
CC
0.2
V, CE
2
< 0.2 V
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V
f = f
max
(address and data only),
f = 0 (OE and WE), V
CC
= 3.60 V
I
SB2[7]
Automatic CE power-down
current – CMOS inputs
CE
1
> V
CC
– 0.2 V, CE
2
< 0.2 V
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= 3.60 V
–
1
4
µA
Notes
3. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
4. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a 100 µs ramp time from 0 to V
CC(min)
and 200 µs wait time after V
CC
stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
7. Chip enables (CE
1
and CE
2
) must be at CMOS level to meet the I
SB1
/ I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Document Number: 38-05579 Rev. *O
Page 4 of 19
CY62128EV30 MoBL
®
Capacitance
Parameter
[8]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter
[8]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
32-pin TSOP I
56.90
14.81
32-pin SOIC
79.34
18.49
32-pin STSOP Unit
69.47
13.39
°C/W
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
30 pF
INCLUDING
JIG AND
SCOPE
R2
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THEVENIN
EQUIVALENT
OUTPUT
R
TH
V
TH
Parameters
R1
R2
R
TH
V
TH
2.50 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
Unit
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05579 Rev. *O
Page 5 of 19
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