Triple, 180° Out-of-Phase, Synchronous Step-Down
PWM Controller
ISL9443
The ISL9443 is a triple-output synchronous buck controller that
integrates three PWM controllers which are fully featured and
designed to provide multi-rail power for use in products such as
cable and satellite set-top boxes, VoIP gateways, cable modems,
and other home connectivity products as well as a variety of
industrial and general purpose applications. Each output is
adjustable down to 0.7V. The PWMs are synchronized at 180°
out-of-phase, thus reducing the input RMS current and ripple
voltage.
The ISL9443 offers programmable soft-start and tracking
functions for ease of supply rail sequencing and integrated
UV/OV/OC/OT protections in a space conscious 5mmx5mm QFN
package.
Switching frequency can be set between 200kHz and 1200kHz
using a resistor. The ISL9443 can be synchronized to an external
clock to reduce beat frequencies.
The ISL9443 utilizes internal loop compensation to keep
minimum peripheral components for a compact design and a
low total solution cost. The controller is implemented with
current mode control with feed forward to cover various
applications even with fixed internal compensation.
Features
• Three Integrated Synchronous Buck PWM Controllers
- Internal Bootstrap Diodes
- Independent Programmable Output Voltage
- Independent Soft-Starting and Tracking
• Power-Good Indicator
• Light Load Efficiency Enhancement
- Low Ripple Diode Emulation Mode with Pulse Skipping
• Supports Pre-Biased Output
• Programmable Frequency: 200kHz to 1200kHz
• Adaptive Shoot-Through Protection
• Out-of-Phase Switching (0°/180°/0°)
• No External Current Sense Resistor
- Uses Lower MOSFET’s r
DS(ON)
• Complete Protection
- Overcurrent, Overvoltage, Over-Temperature
• Wide Input Voltage Range: 4.5V to 28V
• Pb-Free (RoHS Compliant)
Related Literature
• Technical Brief
TB389
“PCB Land Pattern Design and Surface
Mount Guidelines for QFN (MLFP) Packages”
Applications
• VoX Gateway Devices
• NAS/SAN Devices
• ATX power supplies
+12V
+
CIN1
CIN2
0.1µF
VOUT1
+1.0V, 6A
CO1
100µF
+
L1
1.0µH
RESN1
1.3kΩ
ISEN1
+12V
C1
4.7µF
VIN
VCC_5V
CB1
LGATE1
PHASE1
BOOT1
UGATE1
UGATE2
BOOT2
PGND
0.1µF
CB2
PHASE2
LGATE2
ISEN2
FB2
+12V
UGATE3
RESN2
1.3kΩ
R9
11.5kΩ
Q1
Q2
L2
2.2µH
VOUT2
+3.3V,6A
+
CO2
100µF
R8
3.09kΩ
R4
15.8kΩ
ISL9443
EN23
MODE/SYNC
FB1
OCSET1
OCSET2
OCSET2
SGND
BOOT3
PHASE3
TK/SS2,3
LGATE3
FB3
ISEN3
CB3
0.1µF
Q3
L3
3.3µH
VOUT3
+5.0V,6A
+
CO3
100µF
R3
31.6kΩ
RT
RT
49.9kΩ
EN/SS1
CSS
10nF
PGOOD
RESN3
1.3kΩ
R4
10.7kΩ
R3
1.74kΩ
R5
100kΩ
R6
200kΩ
R7
200kΩ
FIGURE 1. TYPICAL APPLICATION
February 24, 2012
FN7663.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9443
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL9443IRZ
NOTES:
1. Add “-T*” for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL9443.
For more information on MSL please see techbrief
TB363.
PART
MARKING
ISL9443 IRZ
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
32 Ld 5x5 QFN
PKG.
DWG. #
L32.5X5B
Pin Configuration
ISL9443
(32 LD 5x5 QFN)
TOP VIEW
PHASE1
PHASE2
25
UGATE1
UGATE2
27
LGATE1
LGATE2
BOOT1
BOOT2
26
32
31
30
29
28
ISEN1
VCC_5V
VIN
EN/SS1
FB1
OCSET1
RT
PGOOD
1
2
3
4
5
6
7
8
9
EN23
10
SGND
11
OCSET2
12
FB2
13
TK/SS2
14
OCSET3
15
FB3
16
TK/SS3
24
23
22
21
20
19
18
17
ISEN2
PGND
LGATE3
UGATE3
BOOT3
PHASE3
ISEN3
MODE/SYNC
Pin Descriptions
PIN
1
2
NAME
ISEN1
VCC_5V
FUNCTION
Current signal input for PWM1. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
Output of the internal 5V linear regulator. This output supplies bias for the IC, the low side gate drivers, and the external
boot circuitry for the high-side gate drivers. The VCC_5V pin must be always decoupled to power ground with a minimum
of 4.7µF ceramic capacitor, placed very close to the pin. Do not allow the voltage at VCC_5V to exceed VIN at any time.
This pin should be tied to the input rail. It provides power to the internal linear drive circuitry and is also used by the feed-
forward controller to adjust the amplitude of each PWM sawtooth. Decouple this pin with a small ceramic capacitor
(0.1µF to 1µF) to ground.
This pin provides an enable/disable function and soft-starting for PWM1 output. The output is disabled when the pin is
pulled to GND. During start-up, a regulated 1.55µA soft-start current charges an external capacitor connected at this pin.
When the voltage on the EN/SS1 pin reaches 1.3V, the PWM1 output becomes active. From 1.3V to 2.0V, the reference
voltage of the PWM1 is clamped to the voltage at EN/SS1 minus 1.3V. The capacitance of the soft-start capacitors sets
the soft-starting time and enable delay time. Setting the soft-starting time too short might create undesirable overshoot
at the output during start-up. VCC_5V UVLO discharges the EN/SS1 via an internal MOSFET.
3
VIN
4
EN/SS1
2
FN7663.1
February 24, 2012
ISL9443
Pin Descriptions
PIN
5
6
7
NAME
FB1
OCSET1
RT
(Continued)
FUNCTION
PWM1 feedback input. Connect FB1 to a resistive voltage divider from the output of PWM1 to GND to adjust the output
voltage.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM1.
A resistor from this pin to ground adjusts the switching frequency from 200kHz to 1.2MHz.
R
T
=
(
23.36
× (
1.5
×
t
SW
–
0.36
) ) ⋅
kΩ
Where t
SW
is the switching period in µs.
(EQ. 1)
8
9
10
PGOOD
EN23
SGND
Open drain logic output used to indicate the status of the PWM output voltages. This pin is pulled LOW when any of the
outputs is not within ±11% of the nominal voltage.
Enable/Disable input for PWM2 and PWM3. The outputs of PWM2 and PWM3 are enabled when this pin is pulled HIGH,
and disabled when this pin is pulled LOW. Do not float this pin.
This is the small-signal ground common to all 3 controllers. It is suggested to route this separately from the high current
ground (PGND). SGND and PGND can be tied together if there is one solid ground plane with no noisy currents around
the chip. All voltage levels are measured with respect to this pin.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM2.
PWM2 feedback input. Connect FB2 to a resistive voltage divider from the output of PWM2 to GND to adjust the output
voltage.
Dual function pin. The reference voltage of PWM2 is clamped to the voltage at TK/SS2 during start-up. When this pin is
used for tracking, another channel is configured as the master and the output voltage of the master channel is applied
to this pin via a resistor divider.
When used for soft-starting control, a soft-start capacitor is connected from this pin to GND. A regulated 1.55µA soft-starting
current charges up the soft-start capacitor. Value of the soft-start capacitor sets the PWM2 output voltage ramp.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM3.
PWM3 feedback input. Connect FB3 to a resistive voltage divider from the output of PWM3 to GND to adjust the output
voltage.
Dual function pin. The reference voltage of PWM3 is clamped to the voltage at TK/SS3 during start-up. When this pin is
used for tracking, another channel is configured as the master and the output voltage of the master channel is applied
to this pin via a resistor divider.
When used for soft-starting control, a soft-start capacitor is connected from this pin to GND. A regulated 1.55µA soft-starting
current charges up the soft-start capacitor. Value of the soft-start capacitor sets the PWM3 output voltage ramp.
Dual function pin. Tie this pin to ground or VCC_5V for DEM or CCM operation mode selection. Connect this pin to ground
to select Diode Emulation Mode with pulse skipping at light load. While connected to VCC_5V, the controllers operate in
PWM Mode at light load.
Connect this pin to an external clock for synchronization. The controller operates in PWM mode at light load when
synchronized with an external clock.
Current signal input for PWM3. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
Phase node connection for PWM3. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE3 is the internal lower supply rail for UGATE3.
Bootstrap pin to provide bias for PWM3 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
High-side MOSFET gate driver output for PWM3.
Low-side MOSFET gate driver output for PWM3.
Power ground connection for all three PWM channels. This pin should be connected to the sources of the lower MOSFETs
and the (-) terminals of the external input capacitors
Current signal input for PWM2. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
Phase node connection for PWM2. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE2 is the internal lower supply rail for UGATE2.
11
12
13
OCSET2
FB2
TK/SS2
14
15
16
OCSET3
FB3
TK/SS3
17
MODE/SYNC
18
19
20
21
22
23
24
25
ISEN3
PHASE3
BOOT3
UGATE3
LGATE3
PGND
ISEN2
PHASE2
3
FN7663.1
February 24, 2012
ISL9443
Pin Descriptions
PIN
26
27
28
29
30
31
32
-
NAME
BOOT2
UGATE2
LGATE2
LGATE1
UGATE1
BOOT1
PHASE1
EPAD
(Continued)
FUNCTION
Bootstrap pin to provide bias for PWM2 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
High-side MOSFET gate driver output for PWM2.
Low-side MOSFET gate driver output for PWM2.
Low-side MOSFET gate driver output for PWM1.
High-side MOSFET gate driver output for PWM1.
Bootstrap pin to provide bias for PWM1 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
Phase node connection for PWM1. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE1 is the internal lower supply rail for UGATE1.
EPAD at ground potential. Solder it directly to GND plane for better thermal performance.
4
FN7663.1
February 24, 2012
Block Diagram
BOOT1
VCC_5V
UGATE1
PHASE1
ADAPTIVE DEAD-TIME
VCC_5V
LGATE1
V/I SAMPLE TIMING
ADAPTIVE DEAD-TIME
V/I SAMPLE TIMING
PGOOD
EN23
VIN VCC_5V
VCC_5V
UGATE2
PHASE2
BOOT2
VCC_5V
LGATE2
PGND
POR
PGND
ENABLE
BIAS SUPPLIES
REFERENCE
FAULT LATCH
SOFT-START
EN23
ADAPTIVE DEAD-TIME
V/I SAMPLE TIMING
PHASE3
EN/SS1
VCC_5V
UGATE3
PGND
BOOT3
MODE/SYNC
RT
5
FN7663.1
February 24, 2012
(Note 6)
FB1
180kΩ
1000kΩ
15pF
VCC_5V
LGATE3
ISL9443
_
OCP
+
+ 0.7V
REF
PGND
16kΩ
_
FB3
0.7V REF
TK/SS3
ERROR AMP 1
_
+
PWM1
OC1 OC2 OC3
UV/OV
PWM3
+
EN/SS1
+
1.3V
1.55µA
EN/SS1
FB1 FB2 FB3
OC3
VIN
VCC_5V
ERROR AMP 3
ISEN3
MINIMUM
SOFT-START
ISEN1
CURRENT
SAMPLE
OCSET1
OCSET3
_
+
+
CURRENT
SAMPLE
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
CHANNEL 3
FB2
PWM2
TK/SS2
1.75V REFERENCE
-
+
OC1
SAME STATE FOR
2
CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
ISEN2
OC2
CHANNEL 1
CHANNEL 2
SGND
OCSET2
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