NCP4326
Secondary Controller for
Multi-Output
Quasi-Resonant
Switchmode Power
Supplies
This secondary controller significantly improves the overall
efficiency and cross−regulation figures when used in a Switchmode
Power Supply. Compared to traditional regulation schemes, the
NCP4326 provides superior performance in cross−regulation by
individually regulating outputs. Powered from a main winding, the
device actuates two independent switches that precisely adjust the
considered outputs to resistor−selectable voltages. This controller also
integrates a precision reference voltage, which together with a
dedicated operational amplifier reduces the feedback loop elements to
the minimum. In the end three independent output voltages can be
controlled by a single device.
A skip cycle feature improves the stand by power in light load
condition. Finally, dedicated shutdown pins offer an easy mean to
disable the secondary outputs in applications where a low standby
power performance is key.
Features
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MARKING DIAGRAM
NCP4326DG
AWLYWW
SOIC−16
D SUFFIX
CASE 751B
A
WL
Y
WW
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
PIN CONNECTIONS
CP1
FB1
EN2
CP2
FB2
Ct
Sync
CPm
1
2
3
4
5
6
7
8
(Bottom View)
16
15
14
13
12
11
10
9
EN1
GND
Flux
DRV1
Vcc
DRV2
STBY
FBm
•
•
•
•
•
•
•
•
•
•
•
•
0% to 100% Duty Cycle Range
Integrated Shunt Regulator for Optocoupler Control
Internal Voltage Reference (1.25 V, 1% @ 25°C)
2 Independent Power MOSFET Drivers
Enable/Disable for Each Driver
Independent Soft−Starts on both Output Drivers
Independent Skip Cycle on both Output Drivers
Standby Pin
580 / 650 mA Peak Current Source/Sink Driver Capability
Synchronization Pin
5 V Undervoltage Lock−Out on Vcc
This is a Pb−Free Device
ORDERING INFORMATION
Device
NCP4326DR2G
Package
SOIC−16
(Pb−Free)
Shipping
{
3000 Tape & Reel
Applications
•
Consumer Electronics Applications:
DVD, Set Top Box, CDR, Game Console
•
Any Multi−Output Voltage Quasi−Resonant SMPS
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2009
July, 2009
−
Rev. 2
1
Publication Order Number:
NCP4326/D
NCP4326
Mag
T1
D8
+
L1
C3
2.2 mF
2.2
mH
+
C4
100
mF
GND
D5
DRV1
Q4
+
L2
C5
470
mF
10
mH
Vout_5V
+
C6
100
mF
GND
D6
DRV2
Q5
+
L3
C8
470
mF
10
mH
Vout_3V3
+
C7
100
mF
GND
GND
+ C9
D4
R5
3.32k
R15
1.1k
C13
10 nF
C12
GND
R7
RES1
C14
10 nF
C16
CAP
R10
RES1
C17
CAP
100 nF
U3
NCP4326
CP1
FB1
EN2
CP2
FB2
Ct
SYNC
CPm
EN1
GND
Flux
DRV1
VCC
DRV2
STBY
FBm
16
15
14
13
12
11
10
9
R17
1k
DRV2
STBY
R18
8.66k
DRV1
EN1
C11
100 nF
GND
470
mF
Neg Out
Vout_5V
GND
R14
10k
C10
GND
2.2 nF
VregM
Vout_12V
R8
Vout_3V3
R6
825
EN2
RES1
1
2
3
4
5
R13
511
Mag
GND
VregM
GND
R9
RES1
6
7
8
R16 GND
1k
R11
RES1
C15
10 nF
GND
Figure 1. Typical Application Schematic
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2
NCP4326
Mag
T1
Dem
R3
C1
22
mF
D1
D5
DRV1
D6
C2
220
mF
DRV2
150 1N4148
D8
VregM
+ C3L1 2.2
mH
2.2mF
Q2 + L2 10
mH
C5
470
mF
Q8 + L3 10
mH
C8
470
mF
+ C9
470
mF
Neg Out
R15
1.1k
R8
Q1
Vout_3V3
GND
C13 1
2
3
4
5
6
7
8
GND
+ C4
100uF
+ C6
Vout_12V
GND
Vout_5V
GND
Vout_3V3
GND
D2
P1
R4
15k
R1
39k
Dem
U1
NCP1207A
1 DMG HV 8
2
FB
NC 7
3
4
CS
VCC
6
5
GND DRV
100uF
+
+ C7
100uF
D4
TRANSFO
R5
Vout_5V
3.32k
R17
10k
C10
2.2 nF
GND
C18
47pF
U3
NCP4326
CP1
FB1
EN2
CP2
FB2
Ct
CPm
EN1
GND
Flux
DRV1
VCC
DRV2
FBm
16
15
14
13
12
11
10
9
R12
0R5
R2
4.7k
RES1 10 nF
R6
EN2
C12
825
GND
R7
C14
100 nF
10 nF
RES1
R13
511
GND
R9
RES1
C16
CAP
R10
RES1
C17
CAP
EN1
100 nF
C11
GND
DRV1
DRV2
STBY
Mag
VregM
SYNC STBY
R18
8.66k
GND
U2
SFH6151−2
R16
1k GND
R17
1k
R11
RES1
C15
10 nF
GND
Figure 2. Typical Application Schematic
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3
NCP4326
PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
Symbol
CP1
FB1
EN2
Type
Error Amplifier
Output 1
Voltage
Feedback 1
Soft−Start and
Enable or Disable
the Driver 2
Description
This pin is the output of the error amplifier 1 (monitoring the secondary voltage #1) and is
available for loop compensation purpose.
This is the inverting input of the error amplifier 1. It is connected to the secondary voltage
#1 via a bridge resistor divider.
This pin enables or disables the driver 2. An internal current source with an external
capacitor generates also a soft−start feature for limiting the startup peak current on the
controlled output.
This pin can be left open and by default it enables the driver 2, but without soft−start
feature.
This pin is the output of the error amplifier 2 (monitoring the secondary voltage #2) and is
available for loop compensation purpose.
This is the inverting input of the error amplifier. It is connected to the secondary voltage #2
via a bridge resistor divider.
Connect the timing capacitor between Ct and the ground.
This pin monitors the main secondary winding, detects the beginning and the end of the
demagnetization phase (T
OFF
time on the primary winding) and allows the regulation on
the two secondary outputs.
This pin is the output of the shunt regulator (monitoring the main secondary voltage). An
open collector configuration is implemented.
This is the inverting input of the internal error amplifier. It is connected to the main output
voltage via a bridge resistor divider.
This pin is internally pulled up and allows standby mode feature. This pin can be left open
and by default it enables standard working mode. When this pin is pulled down standby
mode is activated and the quiescent current is reduced to the minimum. The output drivers
are disabled.
This output directly drives the gate of a power MOSFET.
This pin is connected to the main secondary output voltage and internally powers the IC.
This output directly drives the gate of a power MOSFET.
A RC network connected between this pin and a forward winding or a negative output
winding generates the transformer’s flux image. This flux image is compared to a slow
ramp generated on ENx pin for the soft−start Duty Cycle generation controlling the both
outputs.
−
This pin enables or disables the driver 1. An internal current source with an external
capacitor generates also a soft−start feature for limiting the startup peak current on the
controlled output.
This pin can be left open and by default it enables the driver 1, but without soft−start
feature.
4
5
6
7
CP2
FB2
Ct
Sync
Error Amplifier
Output 2
Voltage
Feedback 2
Ct Pin
Synchronization
Pin
Shunt Regulator
Output
Main Voltage
Feedback
Standby
8
9
10
CPm
FBm
STBY
11
12
13
14
DRV2
Vcc
DRV1
Flux
Output Driver 2
Supplies the IC
Output Driver 1
Voltage image of
the magnetic flux
15
16
GND
EN1
The IC ground
Soft−Start and
Enable or Disable
the driver 1
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4
NCP4326
V
DD1
*
V
CC
UVLO
12
V
CC
STBY
Vcc OK
V
CC
V
DD
**
*V
DD1
is not available in standby mode
**V
DD
is available all the time
2V5
1V25
EN1
16
VOLTAGE
REFERENCE
1
CP1
2
FB1
Vcc OK
CHANNEL 1
V
DD1
STBY
+
−
GND
V
DD
I
Ct
CHANNEL 2
2V5
DRV1
13
V
DD1
STBY
10
1V25
4
CP2
5
FB2
DRV
11
6
Ct
V
DD
−
+
GND
GND
Ctramp
Enable or
Int_sync
4V0
1V6
GND
GND
OPAMP with
Open Collector Output
1V25
4V5
Int_Flux
Offset
0V5
V
DD
+
−
GND
8.5R
R
GND
GND
Clamp
0V 1V
EN2
3
GND
15
7
Sync
GND
Flux
14
9
FBm
V
DD1
−
+
GND
8
CPm
CHANNEL x
Int_Flux
V
DD
IENx
ENx
Vcc OK
CPx
V
DD
FBx
1V25
Ctramp
Int_Sync
−
+
GND
V
DD
+
−
GND
LOGIC
LATCH
Figure 3. Internal Circuit Architecture
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5
−
+
V
DD
GND GND
V
CC
5V0
DRVx
GND
STBY
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