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74LCX821 Low Voltage 10-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
January 1996
Revised March 2001
74LCX821
Low Voltage 10-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
General Description
The LCX821 consists of ten D-type Flip-Flops with
3-STATE outputs for bus organized system applications.
The device is designed for low voltage (2.5V or 3.3V) V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX821 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V–3.6V V
CC
specifications provided
s
7.0 ns t
PD
max (V
CC
=
3.3V), 10
µ
A I
CC
max
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
±
24 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human Body Model
>
2000V
Machine Model
>
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX821WM
74LCX821MSA
74LCX821MTC
Package Number
M24B
MSA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
The LCX821 consists of ten edge-triggered flip-flops with
individual D-type inputs with 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The ten flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CLK) transition.
With the Output Enable (OE) LOW, the contents of the ten
flip-flops are available at the outputs. When OE is HIGH,
the outputs go to the high impedance state. Operation of
the OE input does not affect the state of the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74LCX821
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
V
mA
mA
mA
mA
mA
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to V
CC
+
0.5
−
50
−
50
+
50
±
50
±
100
±
100
−
65 to
+
150
°
C
Recommended Operating Conditions
(Note 4)
Symbol
V
CC
V
I
V
O
I
OH
/I
OL
Supply Voltage
Input Voltage
Output Voltage
Output Current
HIGH or LOW State
3-STATE
V
CC
=
3.0V
−
3.6V
V
CC
=
2.7V
−
3.0V
V
CC
=
2.3V
−
2.7V
T
A
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V
−
2.0V, V
CC
=
3.0V
Parameter
Operating
Data Retention
Min
2.0
1.5
0
0
0
Max
3.6
3.6
5.5
V
CC
5.5
Units
V
V
V
±
24
±
12
±
8
−
40
0
85
10
mA
°
C
ns/V
∆
t/
∆
V
Note 2:
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
= −12
mA
I
OH
= −18
mA
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
8 mA
I
OL
=
12 mA
I
OL
=
16 mA
I
OL
=
24 mA
I
I
I
OZ
I
OFF
Input Leakage Current
3-STATE Output Leakage
Power-Off Leakage Current
0
≤
V
I
≤
5.5V
0
≤
V
O
≤
5.5V
V
I
=
V
IH
or V
IL
V
I
or V
O
=
5.5V
Conditions
V
CC
(V)
2.3
−
2.7
2.7
−
3.6
2.3
−
2.7
2.7
−
3.6
2.3
−
3.6
2.3
2.7
3.0
3.0
2.3
−
3.6
2.3
2.7
3.0
3.0
2.3
−
3.6
2.3
−
3.6
0
V
CC
−
0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
±5.0
10
µA
µA
µA
V
V
T
A
= −40°C
to
+85°C
Min
1.7
2.0
0.7
0.8
Max
Units
V
V
3
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74LCX821
DC Electrical Characteristics
Symbol
I
CC
∆I
CC
Parameter
Quiescent Supply Current
Increase in I
CC
per Input
(Continued)
V
CC
(V)
2.3
−
3.6
2.3
−
3.6
2.3
−
3.6
T
A
= −40°C
to
+85°C
Min
Max
10
±10
500
µA
µA
Conditions
V
I
=
V
CC
or GND
3.6V
≤
V
I
, V
O
≤
5.5V (Note 5)
V
IH
=
V
CC
−
0.6V
Units
Note 5:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
V
CC
=
3.3V
±
0.3V
C
L
=
50 pF
Min
f
MAX
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSHL
t
OSLH
t
S
t
H
t
W
Output to Output Skew
(Note 6)
Setup Time, D
n
to CLK
Hold Time, D
n
to CLK
CLK Pulse Width
2.5
1.5
3.3
Output Disable Time
Maximum Clock Frequency
Propagation Delay
CLK to O
n
Output Enable Time
150
1.5
1.5
1.5
1.5
1.5
1.5
7.0
7.0
7.5
7.5
6.5
6.5
1.0
1.0
2.5
1.5
3.3
4.0
2.0
4.0
1.5
1.5
1.5
1.5
1.5
1.5
7.5
7.5
8.0
8.0
7.0
7.0
1.5
1.5
1.5
1.5
1.5
1.5
8.4
8.4
9.8
9.8
7.8
7.8
Max
V
CC
=
2.7V
C
L
=
50 pF
Min
Max
V
CC
=
2.5V
±
0.2V
C
L
=
30 pF
Min
Max
MHz
ns
ns
ns
ns
ns
ns
ns
Units
Note 6:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
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