NCP51401
3 Amp V
TT
Termination
Regulator DDR1, DDR2,
DDR3, LPDDR3, DDR4
The NCP51401 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration.
The NCP51401 maintains a fast transient response and only requires
a minimum output capacitance of 20
mF.
The NCP51401 supports a
remote sensing function and all power requirements for DDR V
TT
bus
termination. The NCP51401 can also be used in low−power chipsets
and graphics processor cores that require dynamically adjustable
output voltages.
The NCP51401 is available in the thermally−efficient DFN10
Exposed Pad package, and is rated both Green and Pb−free.
Features
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DFN10, 3x3, 0.5P
CASE 506CL
MARKING DIAGRAM
51401
ALYWG
G
51401 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
PV
CC
Voltage Range: 1.1 to 3.5 V
Integrated Power MOSFETs
Source and Sink Termination Regulator with Droop Compensation
Fast Load−Transient Response
P
GOOD
− Logic output pin to Monitor V
TT
Regulation
EN − Logic input pin for Shutdown mode
V
RI
− Reference Input Allows for Flexible Input Tracking Either
Directly or Through Resistor Divider
Remote Sensing (V
TTS
)
Built−in Under Voltage Lockout and Over Current Limit
Thermal Shutdown
Small, Low−Profile 10−pin, 3x3 DFN Package
These Devices are Pb−Free and are RoHS Compliant
PIN CONNECTION
V
RI
PV
CC
V
TT
P
GND
V
TTS
1
2
3
4
5
GND
+
10
9
8
7
6
V
CC
P
GOOD
GND
EN
V
RO
Applications
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Chipset/RAM Supplies as Low as 0.5 V
Active Bus Termination
Exposed Pad
ORDERING INFORMATION
Device
NCP51401MNTXG
Package
DFN10
(Pb−Free)
Shipping
†
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
1
May, 2016 − Rev. 0
Publication Order Number:
NCP51401/D
NCP51401
(see notes on page 6)
PIN FUNCTION DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
Pin Name
V
RI
PV
CC
V
TT
P
GND
V
TTS
V
RO
EN
GND
P
GOOD
V
CC
THERMAL
PAD
Pin Function
V
TT
External Reference Input ( set to V
DDQ
/ 2 thru resistor network ).
Power input. Internally connected to the output source MOSFET.
Power Output of the Linear Regulator.
Power Ground. Internally connected to the output sink MOSFET.
V
TT
Sense Input. The V
TTS
pin provides accurate remote feedback sensing of V
TT
. Connect V
TTS
to the
remote DDR termination bypass capacitors.
Independent Buffered V
TT
Reference Output. Sources and sinks over 5 mA. Connect to GND thru
0.1
mF
ceramic capacitor.
Shutdown Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connect
to V
DDQ
for normal operation.
Common Ground.
Power Good (Open Drain output).
Analog power supply input. Connect to GND thru a 1 − 4.7
mF
ceramic capacitor.
Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
vias for maximum power dissipation performance.
ABSOLUTE MAXIMUM RATINGS
Rating
V
CC
, PV
CC
, V
TT
, V
TTS
, V
RI
, V
RO
(Note 1)
EN, P
GOOD
(Note 1)
P
GND
to GND (Note 1)
Storage Temperature
Operating Junction Temperature Range
ESD Capability, Human Body Model (Note 2)
T
STG
T
J
ESD
HBM
Symbol
Value
−0.3 to 6.0
−0.3 to 6.0
−0.3 to +0.3
−55 to 150
150
2000
Unit
V
V
V
°C
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
DISSIPATION RATINGS
Package
10−Pin DFN
T
A
= 255C Power Rating
1.92 W
Derating Factor above
T
A
= 255C
19 mW/°C
T
A
= +855C Power Rating
0.79 W
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2
NCP51401
RECOMMENED OPERATING CONDITIONS
Rating
Supply Voltage
Voltage Range
Symbol
V
CC
V
RO
V
RI
PV
CC
, V
TT
, V
TTS
, EN, P
GOOD
P
GND
Operating Free−Air Temperature
T
A
Value
2.375 to 5.5
−0.1 to 1.8
0.5 to 1.8
−0.1 to 3.5
−0.1 to +0.1
−40 to +125
°C
Unit
V
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
−40°C
≤
T
A
≤
125°C; V
CC
= 3.3 V; PV
CC
= 1.8 V; V
RI
= V
TTS
= 0.9 V; EN = V
CC
; C
OUT
= 3 x 10
mF
(Ceramic); unless otherwise noted.
Parameter
Supply Current
V
CC
Supply Current
V
CC
Shutdown Current
T
A
= +25°C, EN = 3.3 V, No Load
T
A
= +25°C, EN = 0 V, V
RI
= 0 V, No Load
T
A
= +25°C, EN = 0 V, V
RI
> 0.4 V, No Load
V
CC
UVLO Threshold
Wake−up, T
A
= +25°C
Hysteresis
PV
CC
Supply Current
PV
CC
Shutdown Current
V
TT
Output
V
TT
Output Offset Voltage
V
RO
= 1.25 V (DDR1), I
TT
= 0 A
V
RO
= 0.9 V (DDR2), I
TT
= 0 A
PV
CC
= 1.5 V, V
RO
= 0.75 V (DDR3),
I
TT
= 0 A
V
TT
Voltage Tolerance to V
RO
Source Current Limit
Sink Current Limit
V
TT
Rise Time
Discharge MOSFET
On−resistance
V
RI
− Input Reference
V
RI
Voltage Range
V
RI
Input−bias Current
V
RI
UVLO Voltage
EN = 3.3 V
V
RI
rising
Hysteresis
V
RO
− Output Reference
V
RO
Voltage
V
RO
Voltage Tolerance to V
RI
V
RO
Source Current Limit
V
RO
Sink Current Limit
I
RO
=
±10
mA, 0.6 V
≤
V
RI
≤
1.25 V
V
RO
= 0 V
V
RO
= 0 V
−15
10
10
40
40
V
RI
+15
V
mV
mA
mA
V
RI
I
RI
V
RI UVLO
V
RI HYS
360
390
60
0.5
1.8
+1
435
V
mA
mV
−2 A
≤
I
TT
≤
+2 A
V
TTS
= 90% * V
RO
V
TTS
= 110% * V
RO
Enable to V
TT
= 95% of V
RI
, V
TT
has 100
mF
ceramic cap load, V
RI
= 600 mV
V
RI
= 0 V, V
TT
= 0.3 V, EN = 0 V, T
A
= +25°C
R
DIS
V
OS
−15
−15
−15
−25
3
3.5
25
18
+15
+15
+15
+25
4.5
5.5
35
25
mV
A
A
ms
W
mV
T
A
= +25°C, EN = 3.3 V, No Load
T
A
= +25°C, EN = 0 V, No Load
I
PVCC
I
PVCC SHD
V
UVLO
2.15
I
VCC
I
VCC SHD
0.7
65
200
2.3
50
1
0.1
50
50
1
80
400
2.375
V
mV
mA
mA
mA
mA
Conditions
Symbol
Min
Typ
Max
Units
P
GOOD
− Powergood Comparator
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NCP51401
ELECTRICAL CHARACTERISTICS
−40°C
≤
T
A
≤
125°C; V
CC
= 3.3 V; PV
CC
= 1.8 V; V
RI
= V
TTS
= 0.9 V; EN = V
CC
; C
OUT
= 3 x 10
mF
(Ceramic); unless otherwise noted.
Parameter
P
GOOD
Lower Threshold
P
GOOD
Upper Threshold
P
GOOD
Hysteresis
P
GOOD
Start−up Delay
P
GOOD
Leakage Current
P
GOOD
= False Delay
P
GOOD
Output Low Voltage
EN − Enable Logic
Logic Input Threshold
EN Logic high
EN Logic low
Hysteresis Voltage
Logic Leakage Current
Thermal Shutdown
Thermal Shutdown
Temperature
Thermal Shutdown Hysteresis
T
SD
T
SH
150
25
°C
°C
EN pin
EN pin, T
A
= +25°C
V
IH
V
IL
V
ENHYS
I
ILEAK
−1
0.5
+1
1.7
0.3
V
mA
V
Start−up rising edge, V
TTS
within 15% of
V
RO
V
TTS
= V
RI
(P
GOOD
= True)
P
GOOD
= V
CC
+ 0.2 V
V
TTS
is beyond
±20%
P
GOOD
trip thresholds
I
GOOD
= 4 mA
10
0.4
Conditions
(with respect to V
RO
)
(with respect to V
RO
)
Symbol
Min
−23.5%
17.5%
Typ
−20%
20%
5%
2
1
ms
mA
ms
V
Max
−17.5
%
23.5%
Units
V/V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Figure 1. Typical DDR−3 Application Schematic
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NCP51401
General
The NCP51401 is a sink/source tracking termination
regulator specifically designed for low input voltage and
low external component count systems where space is a key
application parameter. The NCP51401 integrates a
high−performance, low−dropout (LDO) linear regulator
that is capable of both sourcing and sinking current. The
LDO regulator employs a fast feedback loop so that small
ceramic capacitors can be used to support the fast load
transient response. To achieve tight regulation with
minimum effect of trace resistance, a remote sensing
terminal, V
TTS
, should be connected to the positive terminal
of the output capacitors as a separate trace from the high
current path from V
TT
.
V
RI
− Generation of Internal Voltage Reference
P
GOOD
de−asserts within 10
ms
after the output exceeds the
limits of the PowerGood window. During initial V
TT
startup, P
GOOD
asserts high 2 ms after the V
TT
enters power
good window. Because P
GOOD
is an open−drain output, a
100 kW, pull−up resistor between P
GOOD
and a stable active
supply voltage rail is required.
The LDO has a constant over−current limit (OCL). Note
that the OCL level reduces by one−half when the output
voltage is not within the power good window. This reduction
is non−latch protection. For V
CC
under−voltage lockout
(UVLO) protection, the NCP51401 monitors V
CC
voltage.
When the V
CC
voltage is lower than the UVLO threshold
voltage, both the V
TT
and V
RO
regulators are powered off.
This shutdown is also non−latch protection.
Thermal Shutdown with Hysteresis
The output voltage, V
TT
, is regulated to V
RO
. When V
RI
is configured for standard DDR termination applications,
V
RI
can be set by an external equivalent ratio voltage divider
connected to the memory supply bus (V
DDQ
). The
NCP51401 supports V
RI
voltage from 0.5 V to 1.8 V,
making it versatile and ideal for many types of low−power
LDO applications.
V
RO
− Reference Output
When it is configured for DDR termination applications,
V
RO
generates the DDR V
TT
reference voltage for the
memory application. It is capable of supporting both a
sourcing and sinking load of 10 mA. V
RO
becomes active
when V
RI
voltage rises to 435 mV and V
CC
is above the
UVLO threshold. When V
RO
is less than 360 mV, it is
disabled and subsequently discharges to GND through an
internal 10 kW MOSFET. V
RO
is independent of the EN pin
state.
EN − Enable Control
If the NCP51401 is to operate in elevated temperatures for
long durations, care should be taken to ensure that the
maximum operating junction temperature is not exceeded.
To guarantee safe operation, the NCP51401 provides
on−chip thermal shutdown protection. When the chip
junction temperature exceeds 150°C, the part will shutdown.
When the junction temperature falls back to 125°C, the
device resumes normal operation. If the junction
temperature exceeds the thermal shutdown threshold then
the V
TT
and V
RO
regulators are both shut off, discharged by
the internal discharge MOSFETs. The shutdown is a
non−latch protection.
Tracking Startup and Shutdown
When EN is driven high, the NCP51401 V
TT
regulator
begins normal operation. When EN is driven low, V
TT
is
discharges to GND through an internal 18−W MOSFET.
V
REF
remains on when EN is driven low.
P
GOOD
− PowerGood
The NCP51401 provides an open−drain P
GOOD
output
that goes high when the V
TT
output is within
±20%
of V
RO
.
The NCP51401 also supports tracking startup and
shutdown when EN is tied directly to the system bus and not
used to turn on or turn off the device. During tracking
startup, V
TT
follows V
RO
once V
RI
voltage is greater than
435 mV. V
RI
follows the rise of V
DDQ
memory supply rail
via a voltage divider. P
GOOD
is asserted 2 ms after V
TT
is
within
±20%
of V
RO
. During tracking shutdown, V
TT
falls
following V
RO
until V
RO
reaches 360 mV. Once V
RO
falls
below 360 mV, the internal discharge MOSFETs are turned
on and quickly discharge both V
RO
and V
TT
to GND.
P
GOOD
is de−asserted once V
TT
is beyond the
±20%
range
of V
RO
.
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